2 Project ideas look fine Group projectsMeetings on FridayShould have signed up.If someone is going to be missing, let us knowProject ideas look fineSafety is going to be a worry this semesterHigh speed things (helicopter blades, other spinney things) either need to be covered so can’t hurt anyone or done outside of lab with reasonable protection (safety glasses) in place.Don’t think anyone has high-power draw issues…Contacted some groups wrt their proposalsMainly with things I want folks thinking about before Friday.
3 Exam is in lecture on Tuesday Some folks will be in conference room in Beyster (CSE).Where everyone will be placed will be sent in an over the weekendClosed book closed notesCan have a calculatorCan’t be a communication device (no cells)May not have notes etc. in it.Any needed document will be provided.Old exams should give a reasonable idea about the exam format and coverage.Exam Q&A Sunday at 3pm, room TBA
4 Topic talks (1/2) 3/12: 3/14: 3/19: 3/21: 3/26: 3/28: 4/2 4/4: DC motor with H-bridgeUltrasonic distance sensors3/14:Can BusVGA3/19:ZigbeeBluetooth3/21:Interaction(s) with camerasKinect3/26:SolderingGps3/28:BANFlash4/2Radiation-hardened processorsEthernetUSBError correcting hardware4/4:Nvidia Low Power Mobile Tegra ProcessorsParallel ProcessingAnalog-to-Digital ConvertersGroup 18
5 Topic talks (2/2)To do:Come to office hours as a group and discuss your topic with me about 2.5 weeks before the presentation.About weeks before the presentation’s scheduled date your group will give a preliminary presentation out-of-class (generally just to the instructor). Feedback will be provided on both technical and non-technical aspects of the talk.About 0.5 weeks beforehand you’ll give a “final” practice version of your talk.Then you’ll have about a 15 minute block in class to give the “real” presentationI’ll have time on Doodle available for groups to do steps 2 and 3.For step 4, come to office hours or grab me after class.
7 Basic categories of memory Read-Only Memory (ROM)Can only be read (accessed)Cannot be written (modified)Contents are often set before ROM is placed into the systemRandom-Access Memory (RAM)Can be read/writtenTerm used for historical reasonsTechnically, ROMs are also random accessVolatile memoryLoses contents when power is lostOften stores program state, stack, and heapIn desktop/server systems, also stores program executableNon-volatile memoryRetains contents when power is lostUsed for boot code in almost every system notice how “wrong” this name is
9 Choosing the right memory requires balancing many tradeoffs Volatility: need to retain state during power down?Cost: wide range of absolute $ and $/bit costsOrganization: 64Kbx1 or 8Kbx8?InterfaceSerial or serial or parallel or parallel or parallel?Synchronous or asynchronous?Access times: critical for high-performanceModify times: critical for write-intensive workloadsErase process: at wire-line speed or 5 minutes in UV?Erase granularity: word, page, sector, chip?
10 Internal organization of memory is usually an array CellwordlinesDifferent memorytypes (e.g. SRAM vsDRAM) aredistinguished by thetechnology used toimplement thememory cell, e.g.:SRAM: 6TDRAM: 1T/1CFrom a chip design viewpoint, what should bethe aspect ratio be?(# rows vs #cols)?From the user’s viewpoint, what should the aspect ratio be?bit lines
12 Physical (on-chip) memory configuration Physical configurations are typically squareSquare minimizes length of (word line + bit line)Shorter length meansShorter propagation timeFaster data accessSmaller trc (read cycle time)Exercise: Assume n2 memory cells configured asn-by-n square array. What is the worst case delay?n2-by-1 rectangular. What is the worst case delay?Exercise: Does wire length dominate access time?Assume propagation speed on chip is 2/3 c (2x10^8 m/s)Assume 1Mbit array is 1 cm x 1 cm
13 Logical (external) memory configuration External configurations are tall and narrowMore address lines (12 to 20+, typically)Fewer data lines (8 or 16, typically)The narrower the configurationThe greater the pin efficiencyAdding one address pin cuts data pins in halfThe easier the data bus routingMany external configurations for given capacity64 Kb = 64K x 1 (16 A + 1 D = 17 pins)64 Kb = 32K x 2 (15 A + 2 D = 17 pins)64 Kb = 16K x 4 (14 A + 4 D = 18 pins)64 Kb = 8K x 8 (13 A + 8 D = 21 pins)64 Kb = 4K x 16 (12 A + 16 D = 28 pins)64 Kb = 2K x 32 (11 A + 32 D = 43 pins)
14 Supporting circuitry is needed to address memory cell and enable reads and writes 2:4 decoderMemoryArray16 bits(4 x 4)4:1 mux/demuxD0A0A1A2A3OE#CS#WE#Control signalsSelect chipSelect memory cellControl read/writeMap internal array toexternal configuration(4x4 16x1)Does mapping of specific address bits to the decoder or mux matter? (hint: think locality)
15 The memory-bus interface Chip Select (CS#)Enables deviceIgnores all other inputs if CS# is not assertedWrite Enable (WE#)Enables write tri-state bufferStore D0 at specified addressOutput Enable (OE#)Enable read tri-state bufferDrive D0 with value at specified address
17 EPROM Erasable Programmable Read-Only Memory Constructed from floating gate FETsCharge trapped on the FG erases cellHigh voltage (13V +) applied to the control gate“Writes” the cell with a 0Allows FG charge to be dissipatedErasing means changing form 0 1Uses UV light (not electrically!)Electrons are trapped on a floating gateWriting means changing from 1 0Erase unit is the whole deviceRetains data for yearsNot used much these daysCostly becauseUse of quartz window (UV transparent)Use of ceramic packagePROM (or OTP) is same, just w/o window
18 Flash Memory Electrically erasable (like EEPROM, unlike EPROM) Used in many reprogrammable systems these daysErase size is block (not word); can’t do byte modificationsErase circuitry moved out of cells to peripherySmaller sizeBetter densityLower costReads are like standard RAMCan “write” bits/words (actually, change from 1 0)Write cycle is O(microseconds)Slower then RAM but faster than EEPROMTo (re)write from 0 1, must explicitly erase entire blockErase is time consuming O(milliseconds to seconds)Floating gate technologyErase/write cycles are limited (10K to 100K, typically)
20 6T is typically used (but has poor density) Fast access times O(10 ns) Static RAMSRAMs are volatileBasic cellBistable core4T: uses pullup resistors for M2, M46T: uses P-FET for M2, M4Access transistorsBL, BL# are provided to improve noise margin6T is typically used (but has poor density)Fast access times O(10 ns)Read/write speeds are symmetricRead/write granularity is word
21 Dynamic RAM Requires only 1T and 1C per cell Outstanding density and low costCompare to the 6T’s per SRAM cellCost advantage to DRAM technologySmall charges involved relatively slowBit lines must be pre-charged to detect bitsReads are destructive; internal writebacks neededGenerally need differential sense amplifiersValues must be refreshed periodicallyPrevents charge from leaking awayComplicates control circuitry slightly
22 Memory mapped I/O and buses Exam coverage (1/2)ARM assemblyCoding; reading ISA entry for an instruction.ABI: writing functions and calling themCaller save, callee save, passing arguments, return values.Misc: Linker, loader, Power-on-reset etc.Memory mapped I/O and busesBasic ideas of why and howSimple bus; AHB; APBWriting code to talk to MMIO devices
23 Exam coverage (2/2) Interrupts Timers Digital logic issues Basics of why and howARM interruptsEnabling, disabling, pending, priority, preemption.What happens on an interrupt in the hardware and how we return.TimersCapture; reference; prescalar; range; resolution.Digital logic issues270 review (set-up/hold time)Glitches and clock synchronization.