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May 9, 20012 Platform Design Considerations Eric Rosario Intel Corporation.

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Presentation on theme: "May 9, 20012 Platform Design Considerations Eric Rosario Intel Corporation."— Presentation transcript:


2 May 9, 20012 Platform Design Considerations Eric Rosario Intel Corporation

3 May 9, 20013 Agenda w Guidelines w Measurement Techniques w Testing Results w Summary

4 May 9, 20014 Guidelines w USB 2.0 guidelines are more systematic, detailed than 1.x whitepapers w The USB 2.0 Platform Design Guideline, Revision 1.0 is available now – w Design Guideline areas: – Board routing, placement and layout guidelines – EMI/EMC solutions – Front panel USB design guidelines

5 May 9, 20015 Board Design w 4 layer sufficient; trace impedance matching is key w Propagation Delay w Maximum Motherboard Trace Length Of 18 Inches – Cable + Traces 18 Inches For Front Panel Solutions Motherboard Is the Toughest Environment Host Controller Delay (3ns) Cable (26ns) Device (1ns) + + + +

6 May 9, 20016 Board Design Guidelines w Board Stack-up: – 4 layer, impedance controlled boards required – Impedance targets must be specified – Ask your board vendor what they can achieve Classic four-layer stack Signal 1 Prepreg VCC Core Ground Prepreg Signal 2 Example target impedance: 0.005 in trace at 60+/-15% 7.5mil traces with 7.5mil 7.5mil traces with 7.5mil spacing Zdiff 90 spacing Zdiff 90

7 May 9, 20017May 17, 20007 Routing Guidelines w Control trace widths to obtain target impedance – Ask your board vendor what they can achieve – As always, cost is a consideration w Maintain strict trace spacing control w Minimize stubs D-D- D+D+ 15k 15k Correct way to connect to resistors

8 May 9, 20018 Motherboard Front Panel Daughter Card Board Design w Daughtercard at front/side panel – Bypass caps, EMI control components, strain relief w Header and cable – Keyed header, cable of limited length and matched impedance Front/Side Panel Connectors

9 May 9, 20019May 17, 20008 Routing Guidelines w Routing over plane splits w Creating stubs with test points w Violating trace spacing guidelines Common Routing Mistakes Ground or power plane tp Dont cross plane splits Proper routing technique maintains spacing guidelines

10 May 9, 2001109 Measurement Techniques w Selecting Appropriate Test Equipment – Accurate measurement of signal quality requires an o-scope and probes with adequate BW and sample rate – Proper test fixtures are also important Equipment that will work Scope: TDS 694C - 10GS/s, 3Ghz Probe: P6247 Fet Probe - 4Ghz,.4pF typ 90 90 Differential Probe

11 May 9, 200111 w USB 2.0 test mode software will be used to enable device and host controller tests w USB 2.0 test fixture will be used to provide ideal termination for signal quality measurement w Differential signaling requires the use of a differential probe HS Relay Differential Probe Test Mode SW USB 2.0 test fixture HS Device Oscilloscope Board Testing

12 May 9, 200112 EMI w USB1.X EMI solutions dont work for USB2 – Low pass filters damage USB 2.0 HS signal quality D+ D - Vcc USB A Connector Typical USB 1.1 Termination Scheme

13 May 9, 200113 EMI w Common mode chokes are a proven USB 2.0 EMI solution – Refer to the USB 2.0 Design Guideline for solutions that work for USB 2.0 FS & HS signal quality requirements Common Mode Chokes are a Defensive Design!!!

14 May 9, 200114 EMI w Proper grounding of chassis is crucial – Connector shell must connect to green wire ground early and well – IO shield must connect securely to chassis and receptacle w 2 wire common mode choke is preferred – Blocks common mode EMI from leaving chassis – Common mode impedance @ 100 Mhz should be < 300 Ohms – Differential Impedance @ 100 Mhz should be < 8 Ohms

15 May 9, 200115 ESD, EMC w ESD strikes spread out in time by inductance of cables and hubs in series – Bypass/flyback caps on Vbus near connector help w Hardware Protection – Well-grounded shield – Common mode choke – Spark gap arrestors – Shielded cables

16 May 9, 200116 DP1 DM1 1.51.551.61.651.71.751.81.851.9 x 10 -5 0 0.5 1 1.5 2 2.5 3 3.5 s V keyboard glitch ESD, EMC w Differential squelch/disconnect w Pattern matching before connectivity w Sampling over extended times e.g. Chirp w Low speed requires cables with at least a foil shield Noise Immunity Built Into Low-Level Protocol

17 May 9, 200117 USB2 Validation Motherboard Front Panel Test Chip Back Panel Test Chip Test Results

18 May 9, 200118 Routing Paths Tested USB Connector Motherboard PCI SLOT LAN South Bridge NECtest chip chip Long Route Front Panel Header Test Results Motherboard PCI SLOT LAN South Bridge USB Connector Short Route NEC test chip

19 May 9, 200119 TP2 TP3 Validation board Results w Back Panel Eye Pattern Results – EMI/ESD components – Both at A-connector (TP2) and at end of USB cable (TP3) (with ideal termination) – Three-stack connector on MB

20 May 9, 200120 18 Shielded, twisted pair 18 ribbon cable Early Testing Results w Front Panel Header Cable Options Tested

21 May 9, 200121 Shielded Front Panel Cable Ribbon Front Panel Cable Validation board Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel ribbon cable

22 May 9, 200122 Validation board Results w Front-panel Cable Implementation Eye Pattern Results – 18 inch, twisted pair, shielded front panel cable – 18 inch unshielded front panel ribbon cable Connector reference 80 72 110 1.4 ns exception window Shielded, Twisted Pair Front Panel Cable 114 145 114 Ribbon Front Panel Cable Connector reference

23 May 9, 200123 Test Results USB 2.0 host controller Back Panel Front Panel USB 2.0 Motherboard

24 May 9, 200124 USB 2.0 Board Test Results w High Speed Back Panel Eye Pattern Results (Figure 1) w High Speed Front Panel Eye Pattern Results with shielded cable (Figure 2) Figure 1 Figure 2

25 May 9, 20012517 Device turns on HS termination Reset USB 2.0 Board Test Results w CHIRP Testing – Measured with single ended probes – At the A-connector (TP2) w Important Parameters – Reset duration – CHIRP K amplitude – CHIRP K duration – HS termination timing – Host CHIRP amplitude

26 May 9, 20012622 Summary w USB 2.0 Design Presents New Challenges – Board layout – Common mode chokes – Front Panel Solutions – Signal Quality Measurement – Compliance Testing w USBIF Is Providing Design Guides In Such Areas

27 May 9, 200127 References w USB-IF – w Platform Design guide – w Contact – – –

28 May 9, 200128 Questions?

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