5 80286 / iAPX 286February 1, 1982Bus Width: 16 bits data, 24 bits address.Included memory protection hardware to support multitasking operating systems with per-process address spaceNumber of Transistors 134,000Addressable memory 16 MB3~6X the performance of the 8086
6 4 independent units: address unit, bus unit, instruction unit and execution unit,which formed a pipeline significantly increasing the performance.In computing, a pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one.The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.
10 …386SXJune 16, 1988a low cost version of the with a 16-bit data bus.The original was subsequently renamed i386DX to avoid confusion.However, Intel subsequently used the 'DX' suffix to refer to the floating-point capability of the i486DX.
11 …386EXIntroduced August 1994Variant of 80386SX intended for embedded systemsStatic core, i.e., may run as slowly (and thus, power efficiently) as desired, down to full haltStatic core is a CPU chip that can be stopped simply by stopping the system clock oscillator that is driving it, and it will hold its state indefinitely and resume processing at the point it was stopped when the clock signal is restarted, as long as it is kept powered.It allows the use of less power, and is suitable for standby mode.
12 Used aboard several orbiting satellites and microsatellites On-chip peripherals:Clock and power managementTimers/countersWatchdog timerSerial I/O units (sync and async) and parallel I/ODMARAM refreshUsed aboard several orbiting satellites and microsatellitesUsed in NASA's FlightLinux project
13 Watchdog – regulator - supervisory body A watchdog timer (or computer operating properly (COP) timer) is a computer hardware or software timer that triggers a system reset or other corrective action,if the main program [due to some fault condition, e.g., a hang] neglects to regularly service the watchdog by writing a "service pulse" to it (aka, "kicking the dog", “petting the dog”, "feeding the watchdog“ or "waking the watchdog").The intention is to bring the system back:from an unresponsive state into normal operation.
14 DMADirect memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the CPU!Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work.With DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done.
15 This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer.Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards.DMA is also used for intra-chip data transfer in multi-core processors.Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel.Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.
16 i386SLThe i386SL was introduced as a power efficient version for laptop computers.The processor offered several power management options (e.g., SMM – System Management Mode), as well as different "sleep" modes to conserve battery power.It also contained support for an external cache of 16 to 64 kB.The extra functions and circuit implementation techniques caused this variant to have over 3 times as many transistors as the i386DX.
17 SMMThe system management mode - is an operating mode in which all normal execution (including the operating system) is suspended, and special separate software (usually firmware or a hardware-assisted debugger) is executed in high-privilege mode.It is intended for use only by system firmware, not by applications software or general-purpose systems software.
18 The first company to design and manufacture a PC based on the Intel was Compaq – the 1st 3rd-party to implement a major technical hardware advance on the PC platform. The 80486 and P5 Pentium line of processors were descendants of the design.
20 ..486DX April ‘89 Bus width – 32 bits No. of transistors – 1.2 million Addressable memory 4 GBVirtual memory 1 TBLevel 1 cache of 8 KB on chipMath coprocessor on chip50X performance of the 8088Used in Desktop computing and servers
21 ..486SXApril ‘91Identical in design to 486DX but without math coprocessor.Used in low-cost entry to 486 CPU desktop computing, as well as extensively used in low cost mobile computing.
25 Pentium with MMX tech. Jan. ‘97 Intel MMX (instruction set) support 16 KB L1 instruction cache16 KB L1 data cacheNumber of transistors 4.5 millionSystem bus clock rate 66 MHz
26 Variants –166, 200 MHz Introduced January 8, 1997233 MHz Introduced June 2, 1997133 MHz (Mobile)166, 266 MHz (Mobile) Introduced January 12, 1998200, 233 MHz (Mobile) Introduced September 8, 1997300 MHz (Mobile) Introduced January 7, 1999
27 32-bit processors: P6/Pentium M microarchitecture
28 Pentium Pro Nov. ‘95 Precursor to Pentium II and III Primarily used in server systems5.5 mil trans.16 KB L1 cache256 KB integrated L2 cache60 MHz system bus clock rate
29 Pentium IIMay 7, 1997Pentium Pro with MMX and improved 16-bit performance242-pin processor packageNumber of transistors 7.5 million32 KB L1 cache512 KB ½ bandwidth external L2 cacheThe only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.
30 Celeron [Pentium II-based] Introduced April 15, 1998242-pin SEPP (Single Edge Processor Package)Number of transistors 7.5 million66 MHz system bus clock rate32 KB L1 cacheNo L2 cacheVariants266 MHz Introduced April 15, 1998300 MHz Introduced June 9, 1998
31 Pentium IIIFeb. ‘99Improved PII, i.e., P6-based core, now including Streaming SIMD Extensions (SSE)Number of transistors 9.5 million512 KB ½ bandwidth L2 External cache242-pin SECC2 (Single Edge Contact cartridge 2) processor packageSystem Bus clock rate 100 MHz, 133 MHz (B-models)
32 Celeron (Pentium III Coppermine-based) Mar. 200028.1 mil trans.66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 200132 kB L1 cache128 kB Advanced Transfer L2 cache
34 Celeron (Pentium III Tualatin-based) 32 KB L1 cache256 KB Advanced Transfer L2 cache100 MHz system bus clock rateFamily 6 model 11Variants1.0 GHz1.1 GHz1.2 GHz1.3 GHz1.4 GHz
35 Pentium M Mar. 2003 64 KB L1 cache 1 MB L2 cache (integrated) Based on Pentium III core, with SSE2 SIMD instructions and deeper pipelineNumber of transistors 77 millionHeart of the Intel mobile Centrino system
37 Celeron M Mar. 2003 64 KB L1 cache 512 KB L2 cache (integrated) SSE2 SIMD instructionsNo SpeedStep technology, is not part of the 'Centrino’ package
38 Intel Core Intel Core Duo T2700 2.33 GHz Intel Core Duo T2600 2.16 GHz Jan. 2006Intel Core Duo T GHzIntel Core Duo T GHzIntel Core Duo T2500 2 GHzIntel Core Duo T2450 2 GHzIntel Core Duo T GHzIntel Core Duo T GHzIntel Core Duo T GHzIntel Core Duo T2300e 1.66 GHzIntel Core Duo T GHzIntel Core Duo L GHz (low voltage, 15W TDP)Intel Core Duo L GHz (low voltage, 15W TDP)Intel Core Duo L GHz (low voltage, 15W TDP)Intel Core Duo U GHz (ultra low voltage, 9W TDP)Intel Core Solo T GHz (533 FSB)Intel Core Solo T GHzIntel Core Solo T GHz