Presentation is loading. Please wait.

Presentation is loading. Please wait.

Manish Kulkarni Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 4/28/20081 Computer Architecture.

Similar presentations


Presentation on theme: "Manish Kulkarni Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 4/28/20081 Computer Architecture."— Presentation transcript:

1 Manish Kulkarni Department of Electrical and Computer Engineering Auburn University, Auburn, AL /28/20081 Computer Architecture & Design (6200) Class Presentation

2 Overview What is CISC and Why to learn? History Architecture Typical x86 design Characteristics & Addressing modes CISC Vs RISC Example Programs The Performance Equation FAQs Recent Developments & Future Scope Resources Questions 4/28/20082 Computer Architecture & Design (6200) Class Presentation

3 What is CISC? Definition: Pronounced "sisk" and standing for Complex Instruction Set Computer, is a Microprocessor Architecture that aims at achieving complex operations with single instructions and favors the richness of the instruction set (typically as many as 200 unique instructions) over the speed with which individual instructions are executed. 4/28/2008 Computer Architecture & Design (6200) Class Presentation3 Why should I know about CISC? Todays computers still use processors which are based on CISC designs It has been a prominent architecture since 1978 Most Emerging Processor designs combine features of CISC and RISC to create better designs.

4 GenerationFirst introduced Prominent Consumer CPU brands linear / physical address space Notable (new) features 1 (IA-16)1978Intel 8086, Intel bit / 20-bit (segmented)first x86 microprocessors Intel 80186, Intel 80188, NEC V20 see above hardware for fast address calculations, fast mul/div etc 21982Intel bit (30-bit virtual) / 24- bit (segmented) MMU, for protected mode and a larger address space 3 (IA-32)1985Intel386, AMD Am bit (46-bit virtual) / 32- bit 32-bit instruction set, MMU with paging 41989Intel486see above RISC-like pipelining, integrated FPU, on-chip cache 51993Pentium, Pentium MMXsee above superscalar, 64-bit databus, faster FPU, MMX 5/61996Cyrix 6x86, Cyrix MIIsee above register renaming, speculative execution 61995Pentium Pro, AMD K5 see above / 36-bit physical (PAE) μ-op translation, PAE (not K5), integrated L2 cache (not K5) History Continued…. 4/28/20084 Computer Architecture & Design (6200) Class Presentation

5 GenerationFirst introduced Prominent Consumer CPU brands linear / physical address space Notable (new) features AMD K6/-2/3, Pentium II/III see above L3-cache support, 3D Now, SSE 71999Athlon, Athlon XPsee above superscalar FPU, wide design (up to three x86 instr./clock) 72000Pentium 4see above deeply pipelined, high frequency, SSE2, hyper- threading 6/7-M2003Pentium Msee aboveoptimized for low power 8 (x86-64)2003Athlon bit / 40-bit physical in first impl. x86-64 instruction set, on- die memory controller 82004Prescottsee above very deeply pipelined, very high frequency, SSE Intel Core, Intel Core 2 see above (some are 32- bit only) low power, multi-core, lower clock frequency AMD Phenomsee above monolithic quad-core, 128 bit FPUs, SSE4a Hyper Transport 3, native memory controller, on-die L3 cache Continued…. 4/28/20085 Computer Architecture & Design (6200) Class Presentation

6 Architecture 4/28/2008 Computer Architecture & Design (6200) Class Presentation6 A typical x86 Architecture Intel 8086 Architecture, the 1 st member of x86 family

7 Characteristics 4/28/2008 Computer Architecture & Design (6200) Class Presentation7 o CISC are Mostly Von Neumann Architecture (There are few exceptions) o Same bus for program memory, data memory, I/O, registers, etc o Generally Micro-coded,Variable length instructions o Segmentation is possible with Segment Register s like DS, ES and an offset which can be common to all segments. o Many powerful instructions are supported, making the assembly language programmers job much easier. o Physical Memory Extension Possible Addressing modes o Register Addressing Mode o Memory Addressing Modes o Displacement Only Addressing Mode o Register Indirect Addressing Modes o Indexed Addressing Modes o Based Indexed Addressing Modes o Based Indexed Plus Displacement Addressing

8 CISC Vs RISC Example Program 4/28/2008 Computer Architecture & Design (6200) Class Presentation8 Main Memory General Purpose Registers ALU

9 4/28/2008 Computer Architecture & Design (6200) Class Presentation9 Consider following task of Multiplication Operands: M[2:3] = operand 1 (15) M[5:2] = operand 2(20) Task : Multiplication Result: M[2:3] <= result

10 The CISC Approach Instruction : MULT 2:3, 5:2 Operations: 1. Loads the two operands into separate registers 2. Multiplies the operands in the execution unit 3. Then stores the product in the some temporary register 4. Stores value back to memory location 2:3 4/28/2008 Computer Architecture & Design (6200) Class Presentation10 MULT is what is known as a "complex instruction." Operates directly on the computer's memory banks Does not require the programmer to explicitly call any loading or storing functions. closely resembles a command in a higher level language. e.g. a C statement "a = a * b."

11 4/28/2008 Computer Architecture & Design (6200) Class Presentation11 The RISC Approach Instructions : LWA, 2:3 LW B, 5:2 MULT A, B SW 2:3, A Operations: 1. Load operand1 into register A 2. Load operand2 into register B 3. Multiply the operands in the execution unit and store result in A 4. Store value of A back to memory location 2:3 These set of Instructions is known as a Reduced Instructions." Cannot Operate directly on the computer's memory banks Requires the programmer to explicitly call any loading or storing functions. RISC processors only use simple instructions that can be executed within one clock cycle

12 CISC RISC Primary goal is to complete a task in as few lines of assembly as possible Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes High cycles per second Variable length Instructions Primary goal is to speedup individual instruction Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Large code sizes Low cycles per second Equal length instructions which make pipelining possible 4/28/2008 Computer Architecture & Design (6200) Class Presentation12

13 The Performance Equation 4/28/2008 Computer Architecture & Design (6200) Class Presentation13 The following equation is commonly used for expressing a computer's performance ability: The CISC approach minimizes the number of instructions per program (2) sacrificing the number of cycles per instruction. (1) RISC does the opposite reduces the cycles per instruction (1) sacrificing number of instructions per program (2) 12

14 FAQs 4/28/2008 Computer Architecture & Design (6200) Class Presentation14 Which one is faster? Well, it is commonly accepted that RISC ISA's should make computers faster. The main reason why is because RISC computers figure out more words in a shorter amount of time due to pipelining. So why isn't my computer a RISC? CISC ISA's were implemented in the first personal computers With more people buying computers, CISC isa's became more prominent Software (especially OS) was developed and "translated" so that personal computers speaking x86 would be able to interact with its users Because there was so much software written for computers "speaking" x86, people continued to buy those computers. If we tried to switch to another ISA, we would not have all of the software choices we have now.

15 4/28/2008 Computer Architecture & Design (6200) Class Presentation15 So why would someone want to develop another ISA? x86 (and CISC) make poor use of the faster hardware we have now. Another problem with x86 is that people have been trying to make it faster for a long time, at least 20 years, and after a while you have found most of the ways to speed the computer up significantly Why don't we just switch to RISC? Although it is not used on your desktop PC, RISC ISA's are implemented in many mainframe computers. Programmers have been trying to make RISC faster for a long time, and they have found many of the areas in which it is able to be sped up significantly.

16 4/28/2008 Computer Architecture & Design (6200) Class Presentation16 Where are we running into problems speeding up RISC and CISC? We are running into problems with speeding up the computer in 2 areas 1.Branching Decisions and predictions consume good amount of processing time 2.Access to memory to fetch instruction and data So What we are going to do?

17 Recent Developments & Future Scope 4/28/2008 Computer Architecture & Design (6200) Class Presentation17 o The terms RISC and CISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. o Modern x86 processors also decode and split more complex instructions into a series of smaller internal "micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions. o Attempts have been made to combine features of both RISC and CISC to develop a new approach o Intel has teamed up with Hewlett-Packard to design a new type of ISA. They are calling it IA-64 (Intel Architecture 64)

18 IA-64 4/28/2008 Computer Architecture & Design (6200) Class Presentation18 What is IA-64? IA-64 is a new instruction set architecture. IA-64 seeks to address: branch delays and memory latency. What main principles is IA-64 designed around? IA-64 seeks to exploit instruction level parallelism to the highest degree. Intel and HP have called their method of exploiting this parallelism in IA-64 EPIC (Explicitly Parallel Instruction Computing). EPIC simulates parallelism by having the compiler find what instructions can be executed in parallel and "explicitly" package them for the CPU. How does IA-64 help with branch delays? IA-64 takes a unique approach of prediction to reduce the consequences of branch delays. The compiler can append a predicate to any instruction it chooses. The compiler will append predicates to instructions that depend on the outcome of a branch in order to help reduce branch penalties.

19 4/28/2008 Computer Architecture & Design (6200) Class Presentation19 How does IA-64 deal with memory latency issues? Memory latency occurs because CPU processing speed is significantly faster than the speed of fetching data from memory. IA-64 suggests a new way to eliminate some memory latency problems, speculative loading. IA-64 Realities: "A study in ISCA '95 by S. Malhlke, et. al. demonstrated that predication removed over 50% of the branches and 40% of the mis-predicted branches from several popular benchmark programs." ( )http://www.hp.com/esy/technology/ia_64/products/isapress.html IA-64 lack compatibility with Intel x86 and HP PA-RISC architectures, so this additional compatibility logic will take lot of die space. Presently, the compilers are in experiment phase and IA-64 has no OS support.

20 Resources 4/28/2008 Computer Architecture & Design (6200) Class Presentation20 o o o 00/risc/risccisc/index.html 00/risc/risccisc/index.html o o o

21 Questions ?? 4/28/2008 Computer Architecture & Design (6200) Class Presentation21


Download ppt "Manish Kulkarni Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 4/28/20081 Computer Architecture."

Similar presentations


Ads by Google