Virtual Memory Paging Fixed size blocks 2-dim address Mapping and address translation Virtual to Physical (v.page no., byte no.) (p.page no., byte no.) PM SM Page no.Byte no.
Virtual Memory Page Tables Logically one per process No. of rows equal no. of pages No. of columns determined by no. of entries (data fields per page) L/NL, M/NM, Page no., SSA, etc. Address translation Active PT, MMU, PTAR
Page Replacement Algorithms The Optimal Page Replacement Algorithm Least Recently Used Least Frequently Used First In First Out – FIFO
Page Replacement Algorithms Second Chance Check referenced bit Clock Circular list with referenced bit Not Recently Used Check referenced and modified bits 4 classes of pages The Working Set The WSClock
Design and Implementation Issues Page size Separate Instruction and Data Spaces Shared Pages Local versus Global Allocation Page Fault Handling Locking Pages in Memory
Segmentation Process divided into logical blocks – segments 2 dim addressing (s.no., byte no) – virtual address Segment Map Table (SMT) is required Variable partition allocation Address Translation VA: (s.no., byte) PA: (partition begin addr., byte) SMTAR Active SMT
Segmentation with Paging Process divided into segments Segments divided into pages Memory allocated as pages VA: (s.no., page no., byte) PA: (page frame no., byte)
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