Presentation on theme: "Dueling Segmented LRU Replacement Algorithm Hongliang Gao Chris Wilkerson."— Presentation transcript:
Dueling Segmented LRU Replacement Algorithm Hongliang Gao Chris Wilkerson
The Basic Ideas Auxiliary Directory: –Evaluates dueling replacement algorithms. Segmented LRU list: –Reference bit protects lines with good locality. –Aging/ Random Promotion. Adaptive Bypass: –Protect cache contents by bypassing the cache completely.
Dueling Replacement Algos 32 sets sampled (static) 2 policies evaluated in each sampled set. 16-bit mini-tags Counter updated when policies differ. Set0 Set1 Set2 Set3 Set4 Set5 Set6 Set7 Tag Array Auxiliary Directory Saturating Counter
Review of Segmented LRU SLRU: Reference Bit 4 LRU bits per line track LRU position Tag Reference bit is marked when a line is referenced. Replace any non-referenced lines first. Replace global LRU if all lines are referenced.
SLRU Features Random Promotion –Reference bit is marked when referenced or when randomly promoted. –Eg: 1/32 newly allocated lines may randomly be selected for promotion. Aging –Reference bits can be cleared as well as set. –Line allocations cause the reference bit of the LRU line to be cleared.
Adaptive Bypass Bypass based on a random probability. –Eg: 1, 1/2, 1/4, … 1/4096. –Probability is doubled/halved according to the success of previous bypasses. Data Structure w/ Bypassw/o Bypass Misses result in allocation or bypass. Thrashing on 4 th wayNo Thrashing Cache
SLRU w/ Adaptive Bypassing De-allocated line tracked by partial tag. Allocated line tracked by 4 bit pointer. Valid Bit Virtual Bypass Bit SLRU: Reference Bit 4 bit pointer for in-cache competitor 16 bit partial tag for out-of-cache competitor
Frequency of Bypass
DSB impact on MPKI vs TLRU MPKI for true LRU % reduction MPKI w/ DSB
SLRU w/ Adaptive Bypassing Bypass Bypassed line tracked by partial tag. Incumbent line tracked by 4 bit pointer. Subsequent reference to bypass line reduces bypass probability. Subsequent reference to incumbent increases bypass probability. SLRU: Reference Bit 4 bit pointer for in-cache competitor 16 bit partial tag for out-of-cache competitor 1 0
Config2: 2 Policies CONFIG 1 CONFIG 2 CONFIG 3 Enable bypassing for policy0True Enable bypassing for policy1FalseTrue Random promotion probability for policy0 000 Random promotion probability for policy Aging for policy0000 Aging for policy1111 Virtual bypassing probability1688 Initial bypassing probability64 8 Second minimum bypassing probability (minimum is 0) 1/2561/4096
Set0 Set1 Set2 Set3 Set4 Set5 Set6 Set7 Tag Array valid bits auxiliary directory collects statistics replacement policy performance and updates a policy selector counter. SLRU 1-reference bit indicates whether each line is in the reference or non-reference list. 4 LRU bits per line track LRU position Tracking bypass 16 bit partial tag for out-of-cache competitor 4 bit pointer for in-cache competitor