2 The Basic Ideas Auxiliary Directory: Segmented LRU list: Evaluates “dueling” replacement algorithms.Segmented LRU list:Reference bit protects lines with good locality.Aging/ Random Promotion.Adaptive Bypass:Protect cache contents by bypassing the cache completely.
3 Dueling Replacement Algos 32 sets sampled (static)2 policies evaluated in each sampled set.16-bit mini-tagsCounter updated when policies differ.Auxiliary DirectorySet0Set1Set2Set3Set4Set5Set6Set7Saturating CounterTag Array
4 Review of Segmented LRU SLRU: Reference Bit4 LRU bits per line track LRU positionTagReference bit is marked when a line is referenced.Replace any non-referenced lines first.Replace global LRU if all lines are referenced.
5 SLRU Features Random Promotion Aging Reference bit is marked when referenced or when randomly promoted.Eg: 1/32 newly allocated lines may randomly be selected for promotion.AgingReference bits can be cleared as well as set.Line allocations cause the reference bit of the LRU line to be cleared.
6 Adaptive Bypass Misses result in allocation or bypass. Thrashing on 4th wayNo ThrashingDataStructurew/o Bypassw/ BypassCacheBypass based on a random probability.Eg: 1, 1/2, 1/4, … 1/4096.Probability is doubled/halved according to the success of previous bypasses.
7 SLRU w/ Adaptive Bypassing SLRU: Reference BitDe-allocated line tracked by partial tag.Allocated line tracked by 4 bit pointer.Valid BitVirtual Bypass Bit1116 bit partial tag for “out-of-cache” competitor4 bit pointer for “in-cache competitor”
12 SLRU w/ Adaptive Bypassing SLRU: Reference BitBypassBypassed line tracked by partial tag.Incumbent line tracked by 4 bit pointer.Subsequent reference to bypass line reduces bypass probability.Subsequent reference to incumbent increases bypass probability.116 bit partial tag for “out-of-cache” competitor4 bit pointer for “in-cache competitor”
13 Config2: 2 Policies CONFIG 1 2 3 Enable bypassing for policy0 True FalseRandom promotion probability for policy0Random promotion probability for policy116Aging for policy0Aging for policy1Virtual bypassing probability8Initial bypassing probability64Second minimum bypassing probability (minimum is 0)1/2561/4096Config2:2 Policies
14 4 LRU bits per line track LRU position auxiliary directory collects statistics replacement policy performance and updates a policy selector counter.SLRU1-reference bit indicates whether each line is in the reference or non-reference list.Set0Set1Set2Set3Set4Set5Set6Set74 LRU bits per line track LRU positionTracking bypassvalid bitsTag Array16 bit partial tag for “out-of-cache” competitor4 bit pointer for “in-cache competitor”