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LIRS : An Efficient Replacement Policy to Improve Buffer Cache Performance Song Jiang 1 and Xiaodong Zhang 1,2 1 College of William and Mary 2 National.

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Presentation on theme: "LIRS : An Efficient Replacement Policy to Improve Buffer Cache Performance Song Jiang 1 and Xiaodong Zhang 1,2 1 College of William and Mary 2 National."— Presentation transcript:

1 LIRS : An Efficient Replacement Policy to Improve Buffer Cache Performance Song Jiang 1 and Xiaodong Zhang 1,2 1 College of William and Mary 2 National Science Foundation

2 The Problem of LRU Replacement File scanning: one-time accessed blocks are not replaced timely; Loop-like accesses: blocks to be accessed soonest can be unfortunately replaced; Accesses with distinct frequencies: Frequently accessed blocks can be unfortunately replaced. Inability to cope with weak access locality

3 Why does LRU Fail Sometimes? A recently used block is not necessarily to be used again soon. Can not deal with working set larger than available cache size

4 LRU Merits Simplicity: affordable implementation Adaptability: responsive to access pattern changes

5 Our Objectives Address the limits of LRU fundamentally. Retain the low overhead and adaptability merits of LRU. Significant efforts have been made to improve LRU, but Case by case; or High runtime overhead Our objectives:

6 Outline Related Work The LIRS Algorithm LIRS Implementation Using LRU Stack Performance Evaluation Sensitivity and Overhead Analysis Conclusions

7 Related Work Aided by user-level hints Detection and adaptation of access regularities Tracing and utilizing deeper history information

8 User-level Hints Application-controlled file caching [Cao et al, USENIX94] Application-informed prefetching and caching [Patterson et al, SOSP96] Rely on users understanding of data access patterns

9 Detection and Adaptation of Regularities SEQ: sequential access pattern detection [Glass et al, Sigmetrics97] EELRU: on-line analysis of aggregate recency distributions of referenced blocks [Smaragdakis et al, Sigmetrics97] DEAR: detection of multiple block reference patterns [Choi et al, USENIX99] AFC: Application/File-level Characterization [Choi et al, Sigmetrics00] UBM: Unified Buffer Management [Kim et al, OSDI00] Case-by-case oriented approaches

10 Tracing and Utilizing Access History LRFU: combine LRU and LFU [Lee et al, Sigmetrics99] LRU-K: replacement decision based on the time of the Kth-to-last reference [ O'Neil et al, Sigmod93] 2Q: use two queues to quickly remove cold blocks [Johnson et al, VLDB94] Either high implementation cost, or workload dependent performance

11 Outline Related Work The LIRS Algorithm LIRS Implementation Using LRU Stack Performance Evaluation Sensitivity and Overhead Analysis Conclusions

12 Observation of Data Flow in LRU Stack Blocks are ordered by recency in the LRU stack; Blocks enter from stack top, and leave from its bottom; A block evicted from the bottom of the stack should have been evicted much earlier ! LRU stack......

13 Inter-Reference Recency (IRR) IRR of a block: number of other unique blocks accessed between two consecutive references to the block. Recency: number of other unique blocks accessed from last reference to the current time IRR = 3 R = 2

14 Principles of Our Replacement If a blocks IRR is high, its next IRR is likely to be high again. We select the blocks with high IRRs for replacement. Once IRR is out of date, we rely on the recency. LIRS: Low Inter-reference Recency Set Replacement Policy We keep the blocks with low IRRs in cache.

15 Basic LIRS Idea: Keep LIR Blocks in Cache Low IRR (LIR) block and High IRR (HIR) block LIR block set (size is L lirs ) HIR block set Cache size L = L lirs + L hirs L hirs L lir s Physical Cache Block Sets

16 An Example for LIRS L lirs =2, L hirs =1 LIR block set = {A, B}, HIR block set = {C, D, E}

17 CDECDE HIR block set ABAB ABAB E LIR block set Resident blocks Mapping to Cache Block Sets L hirs =1 L lirs =2 Physical Cache

18 D is referenced at time 10 The resident HIR block (E) is replaced ! Which Block is replaced ? Replace a HIR Block

19 How LIR Set is Updated ? Recency of LIR Block Used

20 After D is Referenced at Time 10 E is replaced, D enters LIR set

21 If Reference is to C at Time E is replaced, C can not enter LIR set

22 The Power of LIRS Replacement File scanning: one-time accessed blocks will be replaced timely; Loop-like accesses: blocks to be accessed soonest will NOT be replaced; Accesses with distinct frequencies: Frequently accessed blocks will NOT be replaced. Capability to cope with weak access locality

23 Outline Related Work The LIRS Algorithm LIRS Implementation Using LRU Stack Performance Evaluation Sensitivity and Overhead Analysis Conclusions

24 LIRS Efficiency: O(1) Rmax (Maximum Recency of LIR blocks) IRR HIR (New IRR of the HIR block) This efficiency is achieved by our LIRS stack. LRU stack + LIR block with Rmax recency in its bottom ==> LIRS stack.

25 Differences between LRU and LIRS Stacks resident block LIR block HIR block Cache size L = LRU stack LIRS stack L lir = 3 L hir =2 Stack size of LRU decided by cache size, and fixed; Stack size of LIRS decided by LIR block with Rmax recncy, and varied. LRU stack holds only resident blocks; LIRS stack holds any blocks whose recencies are no more than Rmax. LRU stack does not distinguish hot and cold blocks in it; LIRS stack distinguishes LIR and HIR blocks in it, and dynamically maintains their statues.

26 Rmax (Maximum Recency of LIR blocks) IRR HIR (New IRR of the HIR block) Blocks in the LIRS stack ==> IRR < Rmax Other blocks ==> IRR > Rmax LIRS Stack How does LIRS Stack Help?

27 LIRS Operations resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = LIRS stack S 5 3 Resident HIR Stack Q Initialization: All the referenced blocks are given an LIR status until LIR block set is full. We place resident HIR blocks in Stack Q Upon accessing a LIR block (a hit) Upon accessing a resident HIR block (a hit) Upon accessing a non-resident HIR block (a miss)

28 Access a LIR block (a Hit) S 5 3 Q S 5 3 Q Access 4Access 8 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = S 5 3 Q 6 9 SdSd

29 Access a HIR Resident block (a Hit) S 5 3 Q Access 3Access S 5 Q 5 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir = S 5 Q 5 2 SdSd

30 Access a Non-Resident HIR block (a Miss) Access S 7 Q S 5 Q 5 resident in cache LIR block HIR block Cache size L = 5 L lir = 3 L hir =2

31 Access a HIR Non-Resident block (a Miss) (Cont) resident in cache 5 block number LIR block HIR block Cache size L = 5 L lir = 3 L hir =2 Access S 7 Q S 9 Q Access 5 4 S Q

32 Outline Related Work The LIRS Algorithm LIRS Implementation Using LRU Stack Performance Evaluation Sensitivity and Overhead Analysis Conclusions

33 Workload Traces cpp is a GNU C compiler pre-processor trace cs is an interactive C source program examination tool trace. glimpse is a text information retrieval utility trace. postgres is a trace of join queries among four relations in a relational database system sprite is from the Sprite network file system mulit1 is obtained by executing two workloads, cs and cpp, together. multi2 is obtained by executing three workloads, cs, cpp, and postgres, together.

34 Representative Access patterns Looping references: all blocks are accessed repeatedly with a regular interval; Temporally-clustered references: blocks accessed more recently are the ones more likely to be accessed again soon. Probabilistic references: each block has a stationary reference probability, and all blocks are accessed independently with the associated probabilities.

35 Cache Partition 1% of the cache size is for HIR blocks 99% of the cache size is for LIR blocks Performance is not sensitive to a partition.

36 Looping Pattern: cs (Time-space map)

37 Looping Pattern: cs (Hit Rates)

38 Looping Pattern: postgres (Time-space map)

39 Looping Pattern: postgres (Hit Rates)

40

41 Probabilistic Pattern: cpp (Time-space map)

42 Probabilistic Pattern: cpp (Hit Rates)

43 Temporally-Clustered Pattern: sprite (Time-space map)

44 Temporally-Clustered Pattern: sprite (Hit Rates)

45 Mixed Pattern: multi1 (Time-space map)

46 Mixed Pattern: multi1 (Hit Rates)

47 Mixed Pattern: multi2 (Time-space map)

48 Mixed Pattern: multi2 (Hit Rates)

49 Outline Related Work The LIRS Algorithm LIRS Implementation Using LRU Stack Performance Evaluation Sensitivity and Overhead Analysis Conclusions

50 Sensitivity to the Change of L hirs

51

52 LIRS with Limited Stack Sizes

53

54 Conclusions Effectively use deeper access history without explicit regularity detection and high cost operations. Outperform exiting replacement policies. Its implementation as simple as LRU. Applicable to virtual memory and database buffer management.


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