Presentation is loading. Please wait.

Presentation is loading. Please wait.

Yves Leduc, Texas Instruments France, ECOFAC March 2010 1 Prélude.

Similar presentations


Presentation on theme: "Yves Leduc, Texas Instruments France, ECOFAC March 2010 1 Prélude."— Presentation transcript:

1 Yves Leduc, Texas Instruments France, ECOFAC March Prélude

2 Yves Leduc, Texas Instruments France, ECOFAC March Le tempo: 2 mesures répétées 169 fois. Le Boléro de Maurice Ravel, la recette originale dune addiction. En 1927, quand la très célèbre danseuse Ida Rubinstein demanda une pièce de ballet à Maurice Ravel, celui-ci dut résoudre un formidable problème: Comment créer et retenir lattention du public pendant 17 minutes sur une musique de ballet? La solution de Maurice Ravel est devenue lœuvre classique la plus jouée au monde. Parce quelle utilise un mécanisme daddiction implacable. Ida Rubinstein

3 Yves Leduc, Texas Instruments France, ECOFAC March La mécanique dun succès Maurice Ravel propose dabord un thème simple compris de tous. Avant que le public ne se lasse, il propose une nouvelle variante, en ajoutant un instrument. Il prend le soin de soutenir la musique par un tempo particulièrement explicite. Par ce tempo, le public comprend vite quune nouvelle variante va arriver et en devine linstant. Mieux, il apprend à lattendre. Il lattend sans se rendre compte dailleurs que le volume augmente. Le public suit le rythme et se refuse inconsciemment à envisager une fin, une fin pourtant inéluctable. Lorchestre sépoumone, quelques sons discordants et en quelques notes la musique séteint. 18, cest le nombre de variantes que le public a appris à attendre avec impatience.

4 Yves Leduc, Texas Instruments France, ECOFAC March Un succès qui ne peut être eternel Mais la recette de ce succès contient sa fin. Il nest pas possible de répéter cette mécanique à linfini. La musique sarrête, non pas par manque dinspiration mais parce quil nest pas possible daugmenter encore le volume…

5 Yves Leduc, Texas Instruments France, ECOFAC March La mécanique dun succès Maurice Ravel a utilisé une méthode simple qui se décompose en quelques points clés: Proposer quelque chose de simple, facilement compréhensible. Anticiper un besoin de renouveau en proposant juste à temps une variante plus attractive. Augmenter le volume pour satisfaire loreille. Utiliser une cadence rigoureuse pour créer lattente et ne pas décevoir.

6 Yves Leduc, Texas Instruments France, ECOFAC March La loi de Moore ? La loi de Moore serait-elle en fait la loi de Maurice ? La microélectronique est liée à la loi de Moore. Elle doit son succès à un mécanisme très similaire au Boléro de Ravel. Un thème simple, le circuit intégré, compris de tous. Un tempo implacable. De nouvelles fonctions offrant des variantes toujours plus attractives. Avec des performances toujours plus grandes. Et cela à un prix similaire.

7 Yves Leduc, Texas Instruments France, ECOFAC March Un Soupir…

8 Yves Leduc, Texas Instruments France, ECOFAC March Power and Energy Management ECOFAC 2010 Yves Leduc Texas Instruments France Challenge de la conception low power dun point de vue industriel…

9 Yves Leduc, Texas Instruments France, ECOFAC March Waste Consumption Heat High Level Agenda Bill

10 Yves Leduc, Texas Instruments France, ECOFAC March Power I$ a Concern Systems:Power consumption could be simply too much. - Data centers spend twice the money: MW 1 to power the servers 1 to cool the server room - Desk-top computers need fan W Fan is noisy Reliability issue - Mobile phones cannot dissipate more than.. W Sun Black Box

11 Yves Leduc, Texas Instruments France, ECOFAC March Power I$ a Concern ICs:Power consumption could be also too much. - Some package needs heat sink or fan - ICs could run hot and cannot accept new functionalities - Die stacking is limited by power dissipation capability - Current density could be too high for the wiring

12 Yves Leduc, Texas Instruments France, ECOFAC March Power I$ a Concern Home, office: - Standby of household appliances - Low profile cheap appliances in activity waste our money… [ in silence ]

13 Yves Leduc, Texas Instruments France, ECOFAC March Energy I$ a Concern Portable systems:It hurts. - Mobile phones, portable computers,.. must be charged regularly - Pacemakers need battery to be replaced - Energy harvesting systems search for scarce energy - Batteries are heavy, expensive, not reliable… - …

14 Yves Leduc, Texas Instruments France, ECOFAC March Energy I$ a Concern - Standby of household appliances - Low profile cheap appliances in activity Abuse of precious resources all around the world.

15 Yves Leduc, Texas Instruments France, ECOFAC March Energy I$ a Concern Last but not least, world should be green, of course Last but not least, world MUST be green. Doc NASA

16 Yves Leduc, Texas Instruments France, ECOFAC March No Brute Force Solutions Energy ? Batteries. Little hope for a significant breakthrough soon. Fuel cells. They have a small 20% efficiency. 80% heat? Alas… Energy harvesting.An ultra low power niche… Heat Dissipation ? Silicon carbid.Running hot, the heat dissipation is more efficient. Far to be in low cost high volume production. Fluidics to evacuate heat.Expensive! Limited efficiency! Dependability? Power Consumption ? Lower operating voltages.Still no solution to lower voltages in the mV range without speed degradation and good enough noise margin.

17 Yves Leduc, Texas Instruments France, ECOFAC March We have to offer more applications to preserve our business. As our ICs are at the limit of the power dissipation or of the energy consumption, we MUST reduce them to get a chance to add a new application. There is no alternative. Moores Law

18 Yves Leduc, Texas Instruments France, ECOFAC March A Realistic Solution: Energy Aware Design Power Dissipation AND/OR Energy Consumption could be too much. In both cases, LIMITING the energy consumed by the system is the solution. It is all about EFFICIENCY.

19 Yves Leduc, Texas Instruments France, ECOFAC March Tracking Efficiency Everywhere Specifications, Constraints, Expectations, Nice to have … Power Plant Power Distribution Voltage Conversion External Voltage Regulation PCB Routing IC Package Internal Voltage Regulation IC Routing Modules Meaningful Results losses

20 Yves Leduc, Texas Instruments France, ECOFAC March CAUTION WOMEN AT WORK Room for Improvement Everywhere Efficiency is a design care all along the supply chain from the power plant to the expected output. We will review a few area where designers are at work and where innovation is needed. CAUTION MEN AT WORK

21 Yves Leduc, Texas Instruments France, ECOFAC March Power Distribution There are a few ways to distribute electrical power. We tap power from Electrical outlet Primary / secondary battery Inductive coupling and a few others…

22 Yves Leduc, Texas Instruments France, ECOFAC March AC-DC Adapter: transformer or high voltage electronics. A small transformer, such as a plug-in « wall wart »" power adapter commonly used for low-power consumer electronics devices, may be as low as 20% efficient, with considerable energy loss even when not supplying any power to the device. Though individual losses may be only a few watts, it has been estimated that the cumulative loss from such transformers in US alone exceeded 32 TWh in Standby losses must be tracked as a serial killer. Wall wart power adapter Reference and recommended reading: Electrical Outlet

23 Yves Leduc, Texas Instruments France, ECOFAC March [ Interlude ] 1 W all around the year ? 1 instance1 million instances during 1 hour0.001kWh1.0MWh during 1 day0.024kWh24.0MWh during 1 year8.8kWh8.8GWh 32 TWh in US? for 1 person110 kWh 12 W per person all around the year [*] <<<< LOSSES [*] cumulative consumption: home, office,..

24 Yves Leduc, Texas Instruments France, ECOFAC March The Importance of the Scale Effect 12 W all around the year ?with 1 kW at 0.1 i.e a bill of 110 kWh each year per person 1 instance300 million instances during 1 year G <<<< LOSSES It does not hurt too much ? This is a good driver

25 Yves Leduc, Texas Instruments France, ECOFAC March Standby and Idle Mode Power Consumption Standby is activated when an equipment is turned off but the user wants a quick start. In analog, there is no particular difficulty at the exception. For example, of the potential risk of a popping noise in earphones or loudspeakers. In digital, there is a cost associated to save machine states in appropriate registers the states. In software, disk drive or non volatile memories are used to make a snapshot of the system. This potential source of subtle bugs cannot be underestimated. Systems may be in standby mode all around the year with a power consumption ideally at zero. Idle mode. The system must insure a quick wake-up. This mode is much more complex to manage in mobile equipment where significant energy savings are expected. A part of the system, as small as possible, remains active and is responsible for the quick wake-up. State machines managing the idle mode are often very complex, desing of the parts remaining active are challenging.

26 Yves Leduc, Texas Instruments France, ECOFAC March Standby Power Consumption Regulation authorities are driving the power reduction There is no severe technical obstacle to power reduction but there is a COST BARRIER to smash. All products should be designed to minimize the standby power consumption. Regulation authorities have triggered the momentum. Now that this is started, the effort is in the development of low cost techniques. Forgetting the standby power consumption is a BUSINESS KILLER. Customers are becoming sensitive to this specification, although they are not willing to pay more. Being the best on this aspect is becoming smoothly a strong BUSINESS DIFFERENTIATION.

27 Yves Leduc, Texas Instruments France, ECOFAC March Idle Power Consumption Mobile applications are the most active drivers All techniques to reduce losses in a portable device are rapidly implemented. There is a significant R&D effort world-wide on this topic. Leakages in advanced IC technologies impact significantly idle power consumption. This is a formidable challenge that industry is fighting actively on a daily basis.

28 Yves Leduc, Texas Instruments France, ECOFAC March Battery Charger and Battery Management It is all about battery electrochemistry, metrology and energy management Efficiency charger itself is not the main concern as it is plugged to an external source. Precision and Metrology how to estimate precisely the remaining energy in an aging battery idle mode consumption is a severe requirement (battery gauge..) Safety how many are forgetting their charger on an electrical outlet? Integration how to mix power electronics with digital and analog applications

29 Yves Leduc, Texas Instruments France, ECOFAC March A Typical Example: the USB Battery Charger Nokia Travel Charger AC-6 There are a lot of reasons to prefer ONE single good charger to a set of cheap solutions. The battery may be also charged from any USB master. For a design point of view, the USB link is a source of headaches to maintain a good conversion efficiency. But the USB is also an ideal data link to exchange precious information back and forth!

30 Yves Leduc, Texas Instruments France, ECOFAC March Inductive Coupling Efficiency is an obvious design care. New and very exciting developments to come! Inductive Coupling, a Cordless World Palm Touchstone

31 Yves Leduc, Texas Instruments France, ECOFAC March The Root Causes of the Power Consumption The application ! Search for the right algorithms in the right architecture! The active power. CV 2 f represents the activity of the IC. Capacitance C is correlated to the complexity. Higher speed (f) is requiring higher voltage (V 2 ). The static power. Leakages Leakages are larger in advanced process which are used for the largest applications.

32 Yves Leduc, Texas Instruments France, ECOFAC March Operating voltage is an important factor in the power consumption I Limit overdesign ! Clean supplies: power AND ground Use efficient voltage regulators Operating Voltage

33 Yves Leduc, Texas Instruments France, ECOFAC March Overdesign The root causes of overdesign are related to a poor analysis of the market or of the customer requirements, on a loosely defined product or a loose design. The system is targeting too many applications. We have to verify that the most demanding targets are realistic. A system is often overspecified to compensate for the weakness of the analysis. Designers are tempted to build too larger design margins Overdesign has a MAJOR impact to the size and the power consumption of IC modules. Design margins are necessary but should be justified by solid statistical analysis. SO EASY TO UNDERESTIMATE

34 Yves Leduc, Texas Instruments France, ECOFAC March Limit Power Supply Voltage F MAX depends on the gate delay which depends directly on the current in the CMOS gates which depends on the supply voltage. Choose the smallest operating voltage suited to reach specified performances. CMOS gate delay may be approximated in many ways. This is the Taur-Nin model [*] : [*] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge University Press, 1998.

35 Yves Leduc, Texas Instruments France, ECOFAC March Power supply noise limits the IC maximum operating frequency. It is important to stress that, despite a common belief, external bypass capacitors are not effective on all the supply noise bandwidth. This is a deadly MISTAKE. Package is blocking high frequencies. Supplies must be decoupled internally using integrated bypass capacitors. Another belief is that a larger bypass capacitance provides automatically a better decoupling. The power distribution network is a complex RLC structure and is prone to resonances. Power Supply Noise Impact on ICs Performances Fmax 130nm Fmax 90nm Vdrop 90nm 6% 8% 10% 12% 14% 16% 10% 8% 6% 4% 2% 0% 0.0μF 0.2μF 0.4μF 0.6μF 0.8μF 1.0μF speed increase voltage undershoot core capacitance [ Freescale 2006 ]

36 Yves Leduc, Texas Instruments France, ECOFAC March Bad supplies cause IR drop, therefore losses but also produces ringing. Both have to be compensated by larger supply voltages, an additional power consumption. The art or science of decoupling the supplies was the distinctive characteristic of the good electronic engineer. In the microelectronics era, it was stated that this is the reserved domain of the PCB design. It WAS indeed true in the TTL era. This is not true anymore. … Each power supply distribution strip is bypassed with a 100 nF capacitor at the top and bottom. This should provide sufficient bypassing, but in case of suspected problems, you may want to place a 100 nF bypass capacitor at each TTL package. … Clean Supplies

37 Yves Leduc, Texas Instruments France, ECOFAC March Each power supply distribution strip is bypassed with a 100 nF capacitor at the top and bottom. This should provide sufficient bypassing, but in case of suspected problems, you may want to place a 100 nF bypass capacitor at each TTL package.

38 Yves Leduc, Texas Instruments France, ECOFAC March KHz1MHz10MHz100MHz1GHz MHz R target tens of MHz No Bypass Caps 1 Bypass Cap on PCB 10KHz Impedance of a Power Supply Network NB: Noise bandwidth depends on the slopes of signals BW noise 0.35 / slope TTL era Power Supply Impedance Normalized Magnitude Frequency GHz An example of [rough] hierarchical bypassing

39 Yves Leduc, Texas Instruments France, ECOFAC March Bypassing techniques Bypassing techniques are more sophisticated that what we have presented. This is a science. Bypassing strategy, modeling and simulations are possible. But as EDA tools are lagging, brute force simulations are overflowed by the complexity of the designs. This is therefore also an art. Good decoupling not only guarantees a correct functionality but increases the speed that a circuit is able to reach without increasing the supply voltage! This is a distinctive area for differentiation and therefore a confidential topic.

40 Yves Leduc, Texas Instruments France, ECOFAC March Voltage Converter and Regulation Power management is a system in the system. With supply switches, Voltage converters and regulators act as the actuators of the systems power management. DC-DC converters and linear voltage regulators are the typical solutions. Currently, at the exception of low power ICs, the vast majority of the voltage regulation modules are not perfectly integrated as a few external devices still resist to a low cost integration. We have to distinguish the voltage converter which has the main function to convert the voltage with a minimum of losses and the voltage regulator, which has to regulate the output voltage. Both are expected to minimize losses as far as possible.

41 Yves Leduc, Texas Instruments France, ECOFAC March Linear Voltage Regulators The voltage regulator is a kind of bidirectional filter. Low frequency current noise for instance is kicked back to the input. Therefore, linear voltage regulators must be included in the modeling of the power supply network. Models should include their non linear behavior! [ neglecting the regulation! ] R regulator V supply Load V regulated V reference feedback x V regulated

42 Yves Leduc, Texas Instruments France, ECOFAC March Voltage Converters Two major categories: Step-down and step-up DC-DC converters using LC tanks Switched Capacitors DC-DC converters (e.g. voltage doubler,…) The energy density in LC elements is usually not compatible with integration of LC tanks. Integrated solutions are now proposed in some low power mobile applications. Switched capacitors converters are limited to smaller power.

43 Yves Leduc, Texas Instruments France, ECOFAC March DC-DC Converters using LC Tanks Hydraulic Ram One example of Step-up converter (aka Boost Converter) Tip: the hydraulic ram and boost converter are based on a similar idea. In hydraulic analogy, there is no inductor. The water has a significant mass which could store kinetic energy. In electricity the mass of the electron is not significant. A dedicated inductor stores the kinetic energy of the electrical current. L S D C Vout Vbat L S D C Vout Vbat

44 Yves Leduc, Texas Instruments France, ECOFAC March Hydraulic RamDC-DC Boost Converter L S D C Vout Vbat waste water water out feed pipe air L S D C water in

45 Yves Leduc, Texas Instruments France, ECOFAC March DC-DC Converters As DC-DC Converters are based on an energy exchange between the potential energy stored in the capacitor and the kinetic energy stored in the inductor, there is no dissipation but the dissipation due to parasitic resistances, control circuitry and switching scheme inaccuracies. Efficiency is quite good excepted in low current regime. DC-DC converters are among the important modules which are profiting from a healthy R&D work of labs and industry. An example of a step-down & step-up converter [ aka Buck-Boost or SEPIC ] IN OUT

46 Yves Leduc, Texas Instruments France, ECOFAC March The Power Distribution Network [ aka PDN ] From external supply (battery, …) to the internal modules, all the chain must be carefully designed, modeled and simulated. It is impossible to simulate the system at the transistor level. The PDN is including highly non linear modules and resists to accurate linear approximation. It is very difficult to realize a good decoupling to limit noise at an acceptable level. For the power consumption estimation, the modeling and simulation are quite simple. The major issue to get the best compromise between a simple but inefficient architecture and a costly more efficient solution. System partition, IC processes, Power Management, PCB complexity and cost are the major factors to consider. A good PDN is the 1 st condition to keep power consumption under control!

47 Yves Leduc, Texas Instruments France, ECOFAC March The PDN Consumers From specifications, IC processes and current know-how, the voltage of each modules is chosen to the best values. Analog modules are powered by a dedicated network. Supply noise is the major concern. They are traditionally considered as the victims although some class D amplifiers for example could be considered as aggressors. Analog modules are traditionally powered on/off by control signals. Fast digital I/O (like DDR3) are powered by another dedicated network. They are truly aggressors for all other modules. Decoupling is needed! Digital modules are powered by a set of dedicated networks. Each network may be switched on or off to limit power consumption despite high transistor leakages. Voltages may be chosen separately. For SRAM modules in retention mode, the voltage may be lowered to keep the information stored in the array while limiting the power consumption. Internal Busses and Clocks. Heavily loaded, they are significant contributors to the power consumption of a digital IC.

48 Yves Leduc, Texas Instruments France, ECOFAC March The Power Down Issue IC modules may be tricky as the power consumption could depend on the value of external voltages or on external loads. There are a few mistakes to avoid. Internal floating nodes. I/O nodes. Loosely defined system may connect 2 ICs in a wrong way. Hi Z floating node, erratic voltage ON large current Hi Z V SS V DD V SS OK

49 Yves Leduc, Texas Instruments France, ECOFAC March Up A Power Up Issue The IC, of course, has a global reset. Hardware or Software? Lets imagine that a system engineer decides that a software reset is enough. When supplies are activated, the IC is waiting for a software reset. So far so good... The IC is powered on, but its internal bus is idle. The software reset is supposed to be transmitted through the bus to position a control bit somewhere. This control bit will eventually reset the bus? Perhaps not… Supply is OVERLOADED !!! BUS Bus driver 32 bits SHORT CIRCUIT Bus driver at 0 32 bits Bus driver at 1 Hi Z FLOATING BUS, erratic voltage ON VERY large current Bus driver 32 bits

50 Yves Leduc, Texas Instruments France, ECOFAC March nA 1 μA ? 10 pA Soft Floating Node: the Hidden Killer of Analog ICs WpWp WpWp WnWn 10 W n OFF orders of magnitude Voltage is 0 10 pA OFF! WpWp WpWp WnWn 10 W n OFF Solution: ON Due to mismatches, VT n of this transistor could be a few tens of mV smaller than the driver. Current is significantly larger. Due to mismatches, VT p of this transistor could be a few tens of mV smaller than the driver. Current is significantly larger. Voltage could be as large as VT n due to small leakages in drain junctions.

51 Yves Leduc, Texas Instruments France, ECOFAC March Power Management in Large ICs In large ICs like microprocessors, DSPs or SoCs, the power management represents a significant design effort. Power management is often shared by dedicated hardware, embedded software and application. There are at least 4 operating modes: - active mode - idle mode - standby mode - off mode There are several techniques used together to limit the power consumption in each mode. Statistics modeling and simulation are worth to be used. standby idle off active

52 Yves Leduc, Texas Instruments France, ECOFAC March Active Mode For the thermal management, this mode is of course the most demanding. Active mode drains the maximum current from the supplies. Many techniques are used to keep the power consumption to a minimum. [ These techniques will be described later ]

53 Yves Leduc, Texas Instruments France, ECOFAC March Idle Mode Parts of the system are stopped but their information is retained in a fast access memory (SRAM, Flash,..). System is reactivated from time to time to refresh synchronization with external links. The system is supposed to wake up extremely quickly. This mode could be the major contributor to the energy consumption of the system for 3 reasons: - This system is mainly operating in idle mode (e.g. phones) - Real time clock and counters are running. - Process leakage. A good design of the system architecture is key to keep the power consumption to a reasonable value.

54 Yves Leduc, Texas Instruments France, ECOFAC March Standby Mode The system (or part of a system) is stopped but its information is retained in a fast access memory (SRAM, Flash,..). The system needs some time to start-up to resynchronize to external links like RF, ADSL… All combinatorial logic is switched off or at least the clocks are stopped. SRAM are in a retention mode with a supply maintained at a minimal retention voltage. There is no activity. The system is waiting for a software or a hardware on/off command. Leakage control is the main issue. [ It will be described later ]

55 Yves Leduc, Texas Instruments France, ECOFAC March Off Mode Hi Z Although the system is still physically connected to the external supply, it is not supposed to drain any significant current. Previous state of the system may be stored in some non volatile memory (disk drive, flash memory..). There is no activity. The system is waiting for a hardware on/off command. Floating nodes are the traditional killers of the Off Mode esp. in mixed signal modules.

56 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power P = CV 2 f + leakages The product f corresponds to the activity of the system. Architecture and algorithms must be tuned. Supply voltage V is obviously important. Limit overdesign at least! C is the capacitance of active wires, 2 solutions: Process scaling More Moore 3D-ICMore than Moore In the recent CMOS processes, leakages cannot be ignored anymore!

57 Yves Leduc, Texas Instruments France, ECOFAC March High Importance of Algorithms and Architecture There are more expectations to reduce active power by selecting at high level the best algorithms or to use the best hardware solutions. HARDWARE or SOFTWARE? Application specific hardware is always much More efficient. But it is obviously restricted to low level designs by the lack of reconfigurability. FPGA offers some of the expected reconfigurability but performances and cost are deceiving. It exacerbates THE problem of 2D circuits: the weakness of the connection system. Software solutions are very poor performers in speed and power efficiency. Their reconfigurability makes them nevertheless a successful choice.

58 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power by Parallelization The major contributor is the system architecture. This is where efforts should be directed first. A few hints: system architecture, algorithm, data move… Parallel architecture should be preferred, although there is not yet really satisfactory parallelization scheme of serial algorithms 1 wire at Gbits/s 1024 wires at 1 Mbits/s Example: what is the more efficient bus? or

59 Yves Leduc, Texas Instruments France, ECOFAC March Prefer Parallel Solutions, a Simple Example 1 wire at Gbits/s 1024 wires at 1 Mbits/s What is the more efficient bus? Active power Consumption is proportional to: #transitions * C * V 2 [ C of 1 wire ! ] 1 high speed signal 1024 low speed signals lower VDD Active power: lower [Static power: higher]

60 Yves Leduc, Texas Instruments France, ECOFAC March Parallel Solutions ? Not so Simple ! Some applications are obviously parallel. For cost pressure, they have been painfully serialized making real-time software pathetically complex. The power reduction targets are now pushing to parallel processing. - Data transfer, memory, … are making parallel processing very complex. - Cost is another major barrier to parallelization. - Many algorithms are serial by nature. Parallelization is more than challenging. Breakthroughs are still regularly announced… - Multicore processors are replacing single core processor.

61 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power: Process Scaling r channel = … (e/ ε ox ) * l / w c gate = ( ε ox /e) * w * l e l w r c = r c / λ c g= c g / λ r c c g = r c c g / λ ^2 w= w/ λ l= l/ λ e = e/ λ r c = r c c g= c g / λ ^2 r c c g = r c c g / λ ^2 w= w/ λ l= l/ λ e = e [ This is not as good for the connections ]

62 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power:3D-IC More than Moore Die 1 Die 2 Die 3 One Chip >1000s Through Silicon Vias / mm 2 2D - IC 3D - IC Shorter wires Lower capacitances It is all about system partitioning, architecture, business model, cost…

63 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power:Data Transfer LIMIT the transfer of the data ! Significant improvements could be obtained during the design of the high level architecture! SoCs may take profit of differentiated structures. This is a hot subject although a significant breakthrough is still to be found! One example among MANY proposals: Time Triggered Architecture [ aka TTA ]

64 Yves Leduc, Texas Instruments France, ECOFAC March Data Transfer, Minimize Voltage It is important to choose efficient solutions. Overdesign should be avoided! Do not underestimate capacitive coupling between wires! High-Level Interconnect Delay and Power Estimation A. Courtay, O. Sentieys, J. Laurent, and N.Julien Journal of Low Power Electronics Vol. 4, 21–33, 2008 CV2fCV2f

65 Yves Leduc, Texas Instruments France, ECOFAC March feedback supply control Data Transfer, Be Smart CV2fCV2f CRC CRC BER To reduce power, adaptive techniques may also be applied, e.g. Always the right supply. Never higher! But this is costly…

66 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power:the Clocks Clocks are the fastest, the busiest and the most loaded signals of a system. Gated clocks are now well supported by EDA tools and do not represent a design challenge anymore: clocks are distributed only to modules in activity. Clock rates are chosen statically or dynamically to respond to the desired throughput of the IC modules. Clock domains and voltage domains partition system and IC. In some applications, asynchronous logic is preferred. Clock is then used only as time keeper. Real time clock is a low speed and precise clock used for time keeping. Very often, the power consumption of a real time clock is reduced to a bare minimum. Real time clock may be used in idle mode as system clock. Jitter is a killer.

67 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Active Power:DVFS Dynamic Voltage and Frequency Scaling, aka DVFS is the current solution to put the active power consumption of an IC under control! There are a few reasons to modulate the speed of an application. Under hardware control: Limit power consumption by running at the smallest supply voltage Keep the operating temperature of an IC under control Under software control: Limit power consumption by running an application at the right frequency

68 Yves Leduc, Texas Instruments France, ECOFAC March Adaptive Dynamic Voltage and Frequency Scaling Under the control of the hardware, the voltage may be tuned finely, with a relatively fine granularity, to maintain the operation with a minimal supply. This is a dynamic calibration of the performances instead to the traditional calibration of the supply voltage to the specified value. Design is done for typical process parameters with Adaptive DVFS insuring the functionality at the process corners. Design is more aggressive, sizes are smaller, parasitic capacitances are smaller, great factor diminishing the power consumption. On a mobile terminal for instance, the power consumption is a concern per se. All tasks do not need to run at the same speed. It is therefore interesting to limit the operating frequency to the minimum and reduce the supply voltage accordingly. The granularity of Adaptive DVFS may be as small as a module. On a portable computer, the processor[s] may be heavily loaded and temperature could reach critical limits. Slowing down the core and diminishing the supply is an efficient way to bring back the IC to a reasonable temperature. DVFS and Adaptive DVFS are adding more complexity as modules may run asynchronously. Under the control of the application software they are a potential source of bugs.

69 Yves Leduc, Texas Instruments France, ECOFAC March V supply reduction ? Reducing Static Power:Voltage Supply? To reduce the static power consumption, it is tempting to reduce the supply voltage: Leakage is exponentially dependant on the reduction of the threshold voltage. Reduce I Leakage !! To keep performances, threshold voltage should follow the reduction of supply voltage!

70 Yves Leduc, Texas Instruments France, ECOFAC March Reducing Static Power:Reduce leakage! Off mode: the ultimate solution is the power switch. In Standby or Idle mode where data retention is mandatory, 3 solutions: 1.Use high threshold voltage devices where they are not impacting critical paths. 2.Use low supply voltage in retention mode (in SRAM, …) 3.Use dynamic threshold voltage control by back gate biasing (body effect) well V backgate V th

71 Yves Leduc, Texas Instruments France, ECOFAC March Leakages in Nanometric Technologies Device Simulation of Random Dopant Effects in Ultra-small MOSFETs Based on Advanced Physical Models Toriyama, S.; Hagishima, D.; Matsuzawa, K.; Sano, N.; Simulation of Semiconductor Processes and Devices, International Conference on Physical Models, Sept Large Variability! High LEAKAGES Highly UNPREDICTABLE

72 Yves Leduc, Texas Instruments France, ECOFAC March New Transistors ? Hot activity on new concepts! FD SOI FET [1], Double gate FET, FinFET [2], Junctionless Nanowire Transistor [3], Graphene Transistor [4], Carbon Nanotube [5] … With a major target: Improving the ratio ( I on /I off ) None of them are reducing leakages to zero… [1] [2] [3] [4] LETI [5] MIT Tyndal Freescale

73 Yves Leduc, Texas Instruments France, ECOFAC March Leakage is THE problem. Energy management cannot be ignored. Be aggressive. Leakage is THE problem. Power management cannot be ignored. Be smart. Solution below ? Lets Face It. Leakage is a Reality.

74 Yves Leduc, Texas Instruments France, ECOFAC March Conclusion, No Simple and Definitive Solution We can safely state that there is no single solution to power consumption reduction. A continuous effort is required. Power consumption is the other problem of the XXI century. [ Way to success is narrow.. ]

75 Yves Leduc, Texas Instruments France, ECOFAC March Thank you for your attention !


Download ppt "Yves Leduc, Texas Instruments France, ECOFAC March 2010 1 Prélude."

Similar presentations


Ads by Google