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CD4007 CMOS Pairs Electronic Design Laboratory. Overview CD4007 Dual Complementary Pair Plus Inverter Rise Time and Fall Time Design Number Documents.

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Presentation on theme: "CD4007 CMOS Pairs Electronic Design Laboratory. Overview CD4007 Dual Complementary Pair Plus Inverter Rise Time and Fall Time Design Number Documents."— Presentation transcript:

1 CD4007 CMOS Pairs Electronic Design Laboratory

2 Overview CD4007 Dual Complementary Pair Plus Inverter Rise Time and Fall Time Design Number Documents Six Configurations

3 CD4007

4 Reference Inverter and Center Pair

5 Warnings Dont subject CD4007 to high voltages or static electricity. Store CD4007 in an anti-static bag or in anti- static foam. Momentarily touch a metal part of the workbench to discharge yourself before handling the part or touching the leads. Never let voltage on any pin be more positive than pin 14 or more negative than pin 7. The circuit may latch up possibly causing permanent damage.

6 Warnings Always connect pin 7 (substrate for n-channel transistors) to your negative supply voltage and pin 14 (substrate for p-channel transistors) to your positive supply voltage. Connect or turn-on the supply voltages (pins 7 & 14) before any other voltages in your circuit. For added safety, ground any unused inputs.

7 Standard Load -- Pin pF

8 Rise & Fall Time time V OUT 100% 90% 10% 0% Rise Fall

9 Rise Time 47 pF V DD V C (0) = 0 V PLH = 1.29 R onp C r = 2 PLH r = 2.58 R onp C R onp

10 Fall Time 47 pF V C (0) = 5 V PHL = 1.29 R onn C f = 2 PHL f = 2.58 R onn C R onn

11 Design Number Document

12

13 1SP 1DP 1A 1DN 1SN V DD 2A 2DP 2DN V SS 3SP 3A 3Y 3SN

14 2-Input NAND RISE and FALL Worst-Case One Pull up R onp for RISE Worst-Case Two Pull up R onn for Fall V DD

15 Six Configurations Inverter Triple Inverter

16 Six Configurations 3-Input NAND 3-Input NOR

17 Six Configurations OR-AND-INVERT (OAI) OUT = (A+B)C 1Y = (1A+3A)2A

18 Six Configurations Dual Bi-Directional Transmission Gate


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