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SWAN sourcedrain Moores Law No exponential is forever! But can we delay forever?

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SWAN Cavin, Hutchby, Zhirnov, Bourianoff

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SWAN

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Cavin, Hutchby, Zhirnov, Bourianoff

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SWAN DMS: A&M, Maryland, UT MQCA:ND Phasetronics: UT Path Integral Monte Carlo: ASU, UT Pseudospintronics on Graphene: UT, UTD, Maryland Future of Microelectronics: The beginning of the end or the end of the beginning? Sanjay Banerjee, Univ. of Texas Task 5: Nanoscale Characterization UTD Task 4: Nano plasmonic interconnects Rice Task 3: Nanoscale Thermal Management UIUC, NCSU ΓΓK M Phonon Frequency (cm -1 ) Graphene Monolayer Task 2:Spintronics in DMS Task 1: Logic Devices with Alternate State Variables

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SWAN South West Academy of Nanoelectronics Director: S.Banerjee Executive Committee E.Vogel (UTD) A.MacDonald (UT) S. DasSarma (Maryland) W.Porod (Notre Dame) Industrial Mentors: Jeff Welser (IBM) L.Colombo (TI) G. Bourianoff (Intel) G. Carpenter (IBM) MacDonald,Register,Ruoff, Tutuc, Sahu (UT) Vogel, Kim, Kim, Wallace, Cho,Chabal (UTD) Sinova (A&M) Massoud, Halas, Nordlander (Rice) DasSarma (Maryland) Shumway (ASU) Porod, Bernstein (Notre Dame) Pop (UIUC). Kim (NCSU) TI, Intel, IBM, Micron, AMD, Freescale, NIST Texas ETF

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SWAN DNA ~2-1/2 nm diameter Things Natural Things Manmade Fly ash ~ 10-20 m Atoms of silicon spacing ~tenths of nm Head of a pin 1-2 mm Quantum corral of 48 iron atoms on copper surface positioned one at a time with an STM tip Corral diameter 14 nm Human hair ~ 60-120 m wide Red blood cells with white cell ~ 2-5 m Ant ~ 5 mm Dust mite 200 m ATP synthase ~10 nm diameter Nanotube electrode Carbon nanotube ~1.3 nm diameter The Challenge Fabricate and combine nanoscale building blocks to make useful devices, e.g., a photosynthetic reaction center with integral semiconductor storage. Microworld 0.1 nm 1 nanometer (nm) 0.01 m 10 nm 0.1 m 100 nm 1 micrometer ( m) 0.01 mm 10 m 0.1 mm 100 m 1 millimeter (mm) 1 cm 10 mm 10 -2 m 10 -3 m 10 -4 m 10 -5 m 10 -6 m 10 -7 m 10 -8 m 10 -9 m 10 -10 m Visible Nanoworld 1,000 nanometers = Infrared Ultraviolet Microwave Soft x-ray 1,000,000 nanometers = Zone plate x-ray lens Outer ring spacing ~35 nm Office of Basic Energy Sciences Office of Science, U.S. DOE Version 10-07-03, pmd The Scale of Things – Nanometers and More MicroElectroMechanical (MEMS) devices 10 -100 m wide Red blood cells Pollen grain Carbon buckyball ~1 nm diameter Self-assembled, Nature-inspired structure Many 10s of nm More is different! Smaller is different!

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SWAN Subthreshold leakage is diffusion current from S to D (as in BJT) S= ln10 kT/q (1 + C d /C ox )

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SWAN

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Bandstructure effective mass, m *, is inversely related to curvature of bands, and depends on crystal orientation and strain. Density of states m * is related to geometric mean of bandstructure m *. Conductivity m * is harmonic mean of bandstructure m *. Effective

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SWAN Gapless, unless GNR Electric field induced gap in bi-layer Linear E(k) at K point; Dirac massless fermions Min, Sahu, Banerjee, MacDonald, PRB (2007) U ext =0, E gap =0 k space Graphene Bandstructure

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SWAN 0 dI T /dV 0 V I. Spielman et al., Phys. Rev. Lett. 84, 5808 (2000) Charge-neutral superfluid: Bose-Einstein condensate of excitons! Electron-hole pairing enhanced interlayer conductance with NDR Pseudospintronics in Bilayers at low T, high B

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SWAN Atomic Levels: Electrons in Magnetic Field: Electrons in Atomic Orbitals: E0E0 E2E2 E1E1 E3E3 B ħ c Electrons in a Magnetic Field: Landau Levels (Landau levels) E n = (n + 1/2) h c c = eB meme Macroscopic degeneracy: eB/h = 2.42 cm -2 T

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SWAN Resistance Magnetic Field h c B B B I V xy Filling factor = 2 = 1 (von Klitzing, 1980) Quantum Hall Effect

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SWAN The =1 quantum Hall state = 1/2 d ~ l B BCS wave function, manifestly showing the particle-hole pairing in opposite layers: Current carrying state: Equal and opposite currents in the two layers

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SWAN electron precession in magnetic field Spin Precession Starts on application of Magnetic Field B Electron Spin SPIN MAGNETIC MOMENT MAGNETIC FIELD μ X H mħ Polar angles ( θ, φ) H = - μ. B =

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SWAN Quantum 2-Level Systems cos( /2) +sin( /2) e iφ AB top layer: bottom layer:

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SWAN Pseudo-spintronic devices Device consisting of two electron and/or hole layers in close proximity Inter-layer electron-electron interaction strong layer (pseudo-spin) degree of freedom uncertain Charge transport intimately determined by the dynamics of the pseudo-spin degree of freedom zizi zjzj wiwi wjwj = 1/2 d ~ l B

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SWAN Intra-layer vs Inter-layer interaction d E inter = e2e2 d E intra = e2e2 l B E intra E inter d lBlB = Expect exciting physics when d/l b 1 B

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SWAN Quantum Hall Effect-Counterflow transport in GaAs-AlGaAs Vanishing counterflow longitudinal and Hall resistivities at =1 QHS Charge-neutral superfluid: Bose-Einstein condensate of excitons! Electron-hole pairing enhanced interlayer conductance + - I I V xx V xy E. Tutuc et al., Phys. Rev. Lett. 93, 036802 (2004).

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SWAN Graphene bilayer with excitons formed by MOS gate Prediction of above room temperature existence of electron-hole condensate holes in valence band electrons in conduction band Room-Temperature Superfluidity in Graphene Bilayers?, Min, Bistritzer, Su, MacDonaldMinBistritzerSuMacDonald How to make a bilayer exciton condensate flow, Su, MacDonaldSu MacDonald +

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SWAN Bi-layer pseudoSpin Field Effect Transistor (BiSFET) Banerjee, Register, Tutuc and Macdonald Bilayer pseudoSpin Field Effect Transistor (BiSFET): a proposed new logic device S.K. Banerjee, L.F. Register, E.Tutuc, D.Reddy and A. Macdonald., IEEE EDL, accepted (2008); also patent disclosure

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SWAN BisFET simulated output characteristics as a function of interlayer bias and gate bias. VG puts the device in an unbalanced state, leading to lower currents Layer1:Electrons [n] Inter layer bias Many body tunneling Layer2:Holes [p] Bose condensation of excitons [e-h pairs] T c = 0.1E f /k B ; T c = 300K implies n=p=4.9x10 12 cm -2 which is possible by gating Inter layer current

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SWAN Inverter layout with complementary BisFETs and SPICE simulation 1.0 nm EOT, gate L=10 nm, corresponding to the Josephson length, and W=20 nm. Clock frequency= 100 GHz and V clock,peak 25 mV with 2.5 ps rise time. Input and output signals were subject to a fan-in and fan-out of 4 inverters. Current MOSFETs consume ~100 aJ per switching and 2020 end of the roadmap CMOS will consume ~5 aJ [www.itrs.net]. Energy consumed per switching operation per BiSFET= 0.008 aJ! (2X Landauer limit)

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SWAN Clock: – Vlow = 0mV ; Vhigh= 25mV – Rise time= 2.5 ps – Fall time = 2.5 ps – Pulse width = 2.5ps – Pulse period =10 ps – Frequency of cock = 100 GHz – Delay between clock and input signal is 2.5 ps Maximum number of inverters the OR gate can drive: 6 Energy per operation: – For OR GATE (load = 4 inverters) total energy for 4 operations: 133.7 x 1E-21 J – Average Energy per operation 33.4 x 1E-21 J – For NAND GATE(load = 4 inverters) total energy for 4 operations: 121.81x1E-21 J – Average Energy per operation 30.45 x 1E-21 J OR and NAND Gate

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SWAN NAND gate operation

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SWAN The Collective FET vision k B T/nq ~ about 25mV/n

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SWAN Graphene MOSFET Fabrication and Modeling Carrier density in the channel induced by V TG Quantum Capacitance in Graphene V TG and carrier density, n, relation

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SWAN R vs (V TG -V Dirac ) with model: 15nm Al 2 O 3 Top-gated FET Parameters Extracted Values n 0 (cm -2 )3.19– 4.28 x 10 11 Mobility (cm 2 /Vs) 4,434- 6,190 R contact (ohm) 552 - 1579 Thinner dielectric layer lower remote charge impurities in oxide Lower initial carriers less carrier scattering Higher mobility Mobility independent of T Thinner dielectric layer lower remote charge impurities in oxide Lower initial carriers less carrier scattering Higher mobility Mobility independent of T God made solids; surfaces on the other hand are the work of the devil. (Pauli)

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SWAN All Graphene Electronics DARPA Carbon Era Rf Applications (CERA) program with IBM LNA, interconnects, …

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SWAN Tight Binding Model of Graphene Nearest neighbor (NN) tight binding Hamiltonian:, for NN, 0 otherwise. self-consistent potential. Perfect armchair graphene ribbon showing equal no. of atoms in successive slices. Corresponding band structures: No. of atoms in the slice = 7, 8 and 9

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SWAN T(E) vs. E [different roughness (identical W ch )] T(E) vs. E for a 7.63 nm wide graphene channel having different roughness. r = 0.5 » random, r = 1 » perfect.

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SWAN A=0 Precession of phase + C Phasetronics: AB device with Rashba Effect Register, Banerjee Phasetronics: AB device with Rashba Effect Register, Banerjee B=0 EX OR Gate A=0, B=0 C=0 A=0, B=1 C=1 A=1, B=0 C=1 A=1, B=1 C=0 State 0: Electron transmission is suppressedState 1: Electron transmission is permitted

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SWANResonant Injection Enhanced Field-Effect Transistor Patent disclosure, Register, Banerjee

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SWAN ON/OFF states of RIEFET ON state (Vg=150mV in following examples): The multiple quantum-wells below the gate serve as a nearly transparent high- order band pass filter for electrons; OFF state (Vg=0mV): The gate not only raises the channel potential directly beneath the gate relative to the source, but destroys the inter-well resonances and reduce access to the channel even for electrons with sufficient thermal energy. Energy levels of quantum states Aligned Misaligned Transport direction Top gate

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SWAN Spintronics- Datta-Das Transistor Electrons quantum mechanically can be viewed as a spinning top which can point up or down!

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SWAN 1100 A B C Out 110 Binary wire Inverter Majority gate M A B C Programmable 2-input AND or OR gate. Nanomagnet-Based Logic- MQCA Wolfgang Porod and Gary Bernstein, Univ. Notre Dame

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SWAN ITRS, 2005

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SWAN What is needed in the new switch? Speed = CV/I Active Power = CV 2 f Stand-by Power = Sub-V T, gate leakage Desirable Attributes Energy efficiency Speed (performance, noise) Room T operation (non-equilibrium devices?) Size (device/ wafer): capacitance, fan-out Gain; uni-directional signal flow (I/O isolation) Reliability, manufacturability, cost CMOS compatibility (process, topology ) CMOS ca 2020 Energy ~ 10 aJ/op; power~ 10 7 W/cm 2 Energy ~ 10 aJ/op; power~ 10 7 W/cm 2 Speed ~ 0.1 ps/op (10 THz f T ; 100 GHz circuit) Speed ~ 0.1 ps/op (10 THz f T ; 100 GHz circuit) Size ~ L g 5 nm; cell ~ 100 nm, I DN ~ 3 mA/µm Size ~ L g 5 nm; cell ~ 100 nm, I DN ~ 3 mA/µm Density ~ 10 10 cm -2 ; BIT ~100 GBit/ns/cm 2 Density ~ 10 10 cm -2 ; BIT ~100 GBit/ns/cm 2 Cost ~ 10 -12 $/gate Cost ~ 10 -12 $/gate 0.01 aJ/op 100GHz Yes 10 nm, FO=4 ??? Yes ???

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