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Lecture No. 7 Logic Gates By: VISHAL JETHAVA. Recap Integrated Circuits ICs Transistors Implementation technologies Switching speed Power dissipation.

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Presentation on theme: "Lecture No. 7 Logic Gates By: VISHAL JETHAVA. Recap Integrated Circuits ICs Transistors Implementation technologies Switching speed Power dissipation."— Presentation transcript:

1 Lecture No. 7 Logic Gates By: VISHAL JETHAVA

2 Recap Integrated Circuits ICs Transistors Implementation technologies Switching speed Power dissipation Circuit density

3 Recap Implementation Technologies CMOS TTL ECL PMOS & NMOS E 2 CM O S

4 Operational Characteristics DC Supply Voltage Noise Margin Power Dissipation Frequency Response Fan Out

5 TTL Series 74Standard TTL 74SSchottky TTL 74AS Advanced Schottky TTL 74LSLow-Power Schottky TTL 74ALS Advanced Low-Power Schottky TTL 74FFast TTL

6 CMOS Series 5 V CMOS 74HC and 74HCT High-Speed 74AC and 74ACTAdvanced CMOS 74AHC and 74AHCT Advanced High Speed 3.3 V CMOS 74LVLow voltage CMOS 74LVCLow-voltage CMOS 74ALVCAdvanced Low voltage CMOS

7 Noise Margin i/p & o/p signals have a range of voltages Voltage ranges exceeded due to external noise Effect on performance under noisy conditions Margin of error

8 TTL Logic Levels

9 CMOS Logic Levels

10 Unpredictable Behaviour due to Noise

11 Logic Levels and Noise Margin V NH = V OH(min) – V IH(min) V NL = V IL(max) – V OL(max)

12 Logic Levels and Noise Margin CMOS Noise Margins V NH = V OH(min) – V IH(min) = 4.4 - 3.5 = 0.9 v V NL = V IL(max) – V OL(max) = 1.5 – 0.33 = 1.17 v V NH = V OH(min) – V IH(min) = 2.4 – 2.0 = 0.4 v V NL = V IL(max) – V OL(max) = 0.8 – 0.4 = 0.4 v TTL Noise Margins V NH = V OH(min) – V IH(min) = 2.4 - 2.0 = 0.4 v V NL = V IL(max) – V OL(max) = 0.8 – 0.4 = 0.4 v

13 Power Dissipation Power Dissipation constant for TTL Power Dissipation varies with frequency for CMOS

14 TTL Power Dissipation Gate Output High(I CCH ) Gate Output Low(I CCL ) Average Power Dissipated P cc = V cc I cc P cc = V cc (I CCH + I CCL )/2

15 TTL Power Dissipation

16 CMOS Power Dissipation Power Dissipation varies with frequency for CMOS P D = (C PD + C L ).V DD 2.f C PD is the internal power dissipation capacitance C L is the external load dissipation capacitance V DD is the supply voltage f is the transition frequency of the output signal

17 Propagation Delay and Frequency Response Propagation Delay Limits frequencies at which gate can operate

18 Propagation Delay t PHL t PLH

19 Propagation Delay

20 Speed-Power Product (SPP) SPP = t P P D Expressed in Joules (J) units of energy Lower the SP product better is the performance

21 Fan-Out Number of same series gates that a gate can drive. Fan-Out for TTL circuits is fixed Fan-Out for CMOS circuits is related to operational frequency. Fan-Out decreases with increased frequency

22 Fan-Out for TTL Loads Unit Loads = I OH /I IH = I OL /I IL = 400 μA/40 μA = 16 mA/1.6 mA = 10

23 Fan-Out for TTL Loads

24

25 Fan-Out for CMOS Loads

26 TTL Series 7474S74LS74AS74ALS74F Performance Rating Propagation Delay (ns)939.51.743 Power Dissipation (mW)1020281.26 Speed-Power product (pJ) 90601913.64.818 Max. Clock Rate (MHz)351254520070100 Fan-out (same series)1020 402033

27 CMOS Series 74HC74AC74AHC Propagation Delay (ns)1853.7 Power Dissipation (mW) Static0.002750.00550.00275 Power Dissipation (mW) at 100KHz0.06250.080.0625 Speed-Power product (pJ) at 100KHz1.1250.40.23 Max. Clock Rate (MHz)50160170 74LV74LVC74ALVC Propagation Delay (ns)94.33 Power Dissipation (mW) Static0.00160.0008 Max. Clock Rate (MHz)90100150


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