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1 Effects of Parasitic Components in High-Frequency Resonant Drivers for Synchronous Rectification MOSFETs Department of Information Engineering – DEI University of Padova, ITALY Speaker: Giorgio Spiazzi

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2 Outline Review of voltage source driver topologyReview of voltage source driver topology Analysis of resonant voltage source driver topologiesAnalysis of resonant voltage source driver topologies –Unclamped turn-on and clamped turn-off –Clamped turn-on and clamped turn-off –Unclamped turn-on and unclamped turn-off Analysis of parasitic component effectsAnalysis of parasitic component effects

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3 Voltage Source Topology +V dd S1S1 S2S2 R ch M Dissipative driver V gon + R on C + v C (t) i(t) R on = R DSon(S1) +R ch +R g

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4 Possible energy recovery to output in VRM applications Resonant Driver DR1 V dd VoVo + + S1S1 S2S2 D b1 D b2 D c1 L ext M Unclamped turn-on and clamped turn-off

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5 Resonant Driver DR1 Unclamped turn-on and clamped turn-off t ri T on t fu V Con I pk_p V Coff I pk_n t v C (t) i(t) I1I1 T off i g (t) V dd VoVo + + S1S1 S2S2 D b1 D b2 D c1 L ext M vCvC + - i(t)

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6 Resonant Driver DR1 Turn-on phase t ri T on t fu V Con I pk_p V Coff I pk_n t v C (t) i(t) I1I1 T off i g (t) V dd + S1S1 D b1 R DSon C L ext M L int + V Db R Lp RgRg V gon + R on L C + v C (t) i(t) Resonant circuit parameters

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7 Resonant Driver DR1 Inductor current and capacitor voltage Final capacitor voltage If Q on >>1:

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8 Unclamped Resonance 0.2 0.4 0.6 0.8 1 0 0 0.4 0.8 1.2 1.6 2 0 Q = 1000 Q = 10 Q = 5 Q = 2 Q = 1 Q = 0.5 [V N ][I N ] Normalized capacitor voltage and inductor current as a function of o t for different Q values (v C (0) = 0, V N = V gon, I N = V gon /Z o ) T on

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9 Unclamped Resonance 0.2 0.4 0.6 0.8 1 0 1.2 1.4 1.6 1.8 2 1 [V N ] [ ] 0.1110100 Q Normalized final capacitor voltage Normalized final capacitor voltage Ideal performance comparison between a voltage source and an unclamped resonant drivers 0.5

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10 Unclamped Resonance High Q means high L, that means lower resonant frequency, i.e. higher turn on intervalHigh Q means high L, that means lower resonant frequency, i.e. higher turn on interval Minimum loss resistance is the SR gate internal resistance R gMinimum loss resistance is the SR gate internal resistance R g For a voltage source topology:

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11 00.511.522.533.544.55 0.01 0.1 1 10 100 f sw [MHz] R on [ ] Voltage source topology Unclamped resonance topology Q = 4 Q = 2 Q = 1 Maximum R on Q = 0.5 R on_min = 0.05, k = 0.8, R on_min = 1, C = 10nF = 0.05, k = 0.8, R on_min = 1, C = 10nF

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12 V goff + R off -R g L C + v C (t) i(t) RgRg + V Dc i g (t) Resonant Driver DR1 Turn-off phase t ri T on t fu V Con I pk_p V Coff I pk_n t v C (t) i(t) I1I1 T off i g (t) V goff + R off L C + v C (t) i(t)

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13 DR1 Characteristics both switches S 1 and S 2 turn on and off at zero current; the control signals of S 1 and S 2 have no critical timing, the only requirement being to avoid any cross conduction; the switching times of S 1 and S 2 have no influence in the circuit behavior; S 1 and S 2 body diodes are not used (they have high voltage drop and bad reverse recovery behavior); switch lead inductances as well as any parasitic inductance due to traces and layout simply add to the external inductance (they are actually exploited by the circuit); different T on and T off times can be easily achieved; T off interval duration as well as the amount of recovered energy depends on V o value (disadvantage); S 2 command signal must be suitably higher than V o to completely turn it on (disadvantage). No low impedance paths during on and off intervals

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14 Resonant Driver DR2 D c1 and D c2 can be substituted by MOSFETs, thus ensuring a low impedance path to V dd an to ground during on-time and off-time t ri t fi T on T off t fu V Con I pk_p V Coff I pk_n t t ru t fw v C (t) i(t) I2I2 I3I3 i g (t) Clamped turn-on and clamped turn-off +V dd S1S1 S2S2 D c1 D c2 L ext M

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15 V gon + R on L C + v C (t) i(t) V dd + R Lp L C + v C (t) i(t) RgRg + V Dc i g (t) + V D2 V dd + R on -R g L C + v C (t) i(t) RgRg + V Dc i g (t) Resonant Driver DR2 t ri t fi T on T off t fu V Con I pk_p V Coff I pk_n t t ru t fw v C (t) i(t) I2I2 I3I3 i g (t) Turn-on phase

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16 DR2 Characteristics both S 1 and S 2 switches turn on at zero current, but they turn off almost at the inductor peak current; the control signals of S 1 and S 2 have critical timing, having to minimize the freewheeling intervals t fw, in order not to adversely affect the overall efficiency; the switching times of S 1 and S 2 have a great influence on the circuit behavior, causing a significant power loss at turn off (see point 1) as well as increase of T on and T off intervals; S 1 and S 2 body diodes are involved during the recovery of the inductor energy; switch lead inductances as well as any parasitic inductance due to traces and layout have a great impact on the circuit behavior, since they cause high frequency parasitic oscillations at turn off and delay S 1 and S 2 turn off times; V Con value is easily controlled by the supply voltage V dd (advantage)

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17 Resonant Driver DR3 +V dd S1S1 S2S2 D b1 D b2 L ext M Unclamped turn-on and unclamped turn-off T on T off V Con I pk_p V Coff I pk_n t v C (t) i(t)

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18 DR3 Characteristics Same considerations as DR1. Moreover: high V Con values can be achieved with very low supply voltage V dd ; V dd value must be higher than the threshold voltage of S 1 (p-channel MOSFET) in order to fully turn it on; the driver needs some oscillating cycles in order to achieve a steady state operation

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19 Losses Comparison S 1,2 = IRF7319S 1,2 = IRF7319 D b1,2, D cl, and D c1,2 = STPS1L40UD b1,2, D cl, and D c1,2 = STPS1L40U Switching frequency: f sw = 1.8MHzSwitching frequency: f sw = 1.8MHz Maximum diode voltage drop: V Dc = V Db = 0.63VMaximum diode voltage drop: V Dc = V Db = 0.63V External inductance parasitic resistance: R Lp = 200mExternal inductance parasitic resistance: R Lp = 200m External inductance: L ext = 30nH (DR1), L ext = 35nH (DR2), L ext = 30nH (DR3)External inductance: L ext = 30nH (DR1), L ext = 35nH (DR2), L ext = 30nH (DR3) Internal gate resistance: R g = 0.25Internal gate resistance: R g = 0.25 Equivalent gate capacitance: C = 10nFEquivalent gate capacitance: C = 10nF Supply voltage: V dd = 5V (DR1), V dd = 6.8V (DR2), V dd = 3.85V (DR3)Supply voltage: V dd = 5V (DR1), V dd = 6.8V (DR2), V dd = 3.85V (DR3) VRM output voltage for DR1: V o = 1.3VVRM output voltage for DR1: V o = 1.3V Driver parameters:

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20 Losses Comparison: calculations Details of Losses Calculation for DR1 (V Con = 7.41V, L ext = 30nH, V dd = 5V, V o = 1.3V) P dd [mW] P Db1,2 [mW] P Dcl [mW] P R [mW]P o [mW]P Loss [mW] T on, T off [ns] I pk [A] P Tot_loss [mW] Turn on72491142233552.28 502 Turn off1031315321226958.3-2.55 R DS(on) [ ] V D [V] L Sint [nH] L Dint [nH] T sw_off [ns] Q g @ V GS =5V [nC] Q g @ V GS =7V [nC] IRF 7319 p-MOS0.098146321317 n-MOS0.0461461712.516.5 MOSFET S 1 and S 2 parameters

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21 Losses Comparison P dd [mW]P Db1,2 [mW] P R [mW]P Loss [mW] T on, T off [ns]I pk [A]P Tot_loss [mW] Turn on77212627239954.43.16 773 Turn off12624237454.4-3.17 Details of Losses Calculation for DR3 (V Con = 7.44V, V Coff = -3.71V,L ext = 30nH, V dd = 3.85V) (V Con = 7.44V, V Coff = -3.71V, L ext = 30nH, V dd = 3.85V) Details of Losses Calculation for DR2 (V Con = 7.43V, L ext = 35nH, V dd = 6.8V) P dd [mW] P dd_recovered [mW] P D1,2 [mW] P Dcl,2 [mW] P R [mW] P Loss [mW] T on, T off [ns] I pk [A] P Tot_loss [mW] Turn on967179225124129556.13.2 574 Turn off199293621528050.5-3.25

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22 Losses Comparison Driver DR2 losses do not include S 1 and S 2 switching losses: at turn-on: P sw_on = 220mW at turn-off: P sw_off = 135mW Total DR1 losses: P tot_loss = 502mW Total DR2 losses: P tot_loss = 574+355 = 929mW Total DR3 losses: P tot_loss = 773mW

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23 Experimental Waveforms: DR1 v C [2V/div] v Rs [100mV/div] V GS_n-MOS [1V/div] v G_p-MOS [1V/div] v DS_n-MOS [2V/div] With L ext C Load = 10nF (smd), R s = 0.1, U alim = 5V, f sw = 1.8MHz RsRs D cl1 + V Rs + VCVC C

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24 Experimental Waveforms: DR1 v C [2V/div] v Rs [200mV/div] V GS_n-MOS [1V/div] v G_p-MOS [1V/div] v DS_n-MOS [2V/div] Without L ext C Load = 10nF (smd), R s = 0.1, U alim = 5V, f sw = 1.8MHz RsRs D cl1 + V Rs + VCVC C

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25 Experimental Waveforms: DR2 v C [2V/div] v Rs [100mV/div] V GS_n-MOS [2V/div] v G_p-MOS [2V/div] v DS_n-MOS [2V/div] With L ext C Load = 10nF (smd), R s = 0.1, U alim = 7.5V, f sw = 1.8MHz T pNMOS = 58.4ns, T pPMOS = 58.4ns (misurati a 1V)

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26 Experimental Waveforms: DR2 v C [2V/div] v Rs [200mV/div] v G_p-MOS [2V/div] V GS_n-MOS [2V/div] v DS_n-MOS [2V/div] Without L ext C Load = 10nF (smd), R s = 0.1, U alim = 7.5V, f sw = 1.8MHz T pNMOS = 58.4ns, T pPMOS = 58.4ns (misurati a 1V)

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27 Experimental Waveforms: DR3 With L ext v C [2V/div] v Rs [100mV/div] V GS_n-MOS [1V/div] v G_p-MOS [1V/div] v DS_n-MOS [2V/div] C Load = 10nF (smd), R s = 0.1, U alim = 4V, f sw = 1.8MHz

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28 Experimental Waveforms: DR3 Without L ext v C [2V/div] v Rs [200mV/div] V GS_n-MOS [1V/div] v G_p-MOS [1V/div] v DS_n-MOS [2V/div] C Load = 10nF (smd), R s = 0.1, U alim = 4V, f sw = 1.8MHz

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29 Effect of Device Parasitic Capacitances R Lp + vCvC C + L ext i(t) v Cp CpCp + V dd The final capacitor voltage during turn on is lower than expected, especially for driver DR2. Why? Effect of devices output capacitances 0 2 4 6 8 -2 -4 vCvC v DS_n-MOS iLiL [V,A] Time V Con V Coff T on_sw = 150ns X axis scale = 50ns/div 0 2 4 6 8 -2 -4 vCvC v DS_n-MOS iLiL [V,A] Time V Con V Coff T on_sw = 90ns V Con_nominal

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30 Effect of Device Parasitic Capacitances T sw-cond = 60ns T sw-cond = 90ns DR2 Measurements: V dd = 7V, f sw = 1.8MHz, L ext = 0 v c (t) [2V/div] Time [100ns/div]

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31 Effect of Device Parasitic Capacitances DR2: Effect of Switch Conduction Time on V Con and V Coff (V dd = 7V, R s = 0)

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32 DR1 Power Losses at Different V dd (R s = 0, V o = 0)

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33 DR2 Power Losses at Different V dd (R s = 0, T sw-cond = 58.4ns)

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34 DR3 Power Losses at Different V dd (R s = 0)

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35 Internal MOSFET Inductance For the same V dd value, the final V Con voltage without the external inductor L ext in DR1 and DR3 (and, to a less extent, also in DR2) is much lower than the corresponding value with L ext, and this phenomenon is more pronounced at lower V dd valuesFor the same V dd value, the final V Con voltage without the external inductor L ext in DR1 and DR3 (and, to a less extent, also in DR2) is much lower than the corresponding value with L ext, and this phenomenon is more pronounced at lower V dd values This result can be explained only by a lower Q on factor of the circuit without L ext, i.e. a higher R DSon of the p-channel MOSFET S 1 caused by a reduced gate-to-source voltage due to the voltage drop across the internal source inductance (4nH for the IRF7319) that becomes worse at higher di/dt values, i.e. without L ext. This explains why the observed phenomenon is more pronounced at lower V dd values, and justify why DR1, that requires a higher V dd than DR3 to achieve the same V Con value, has lower overall losses than DR3 even without energy recovery.This result can be explained only by a lower Q on factor of the circuit without L ext, i.e. a higher R DSon of the p-channel MOSFET S 1 caused by a reduced gate-to-source voltage due to the voltage drop across the internal source inductance (4nH for the IRF7319) that becomes worse at higher di/dt values, i.e. without L ext. This explains why the observed phenomenon is more pronounced at lower V dd values, and justify why DR1, that requires a higher V dd than DR3 to achieve the same V Con value, has lower overall losses than DR3 even without energy recovery.

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36 Resonant VRM Square-wave operation of the primary half-bridge Zero-voltage and zero-current commutations of SR MOSFETs Q 1 and Q 2 Operation at f s = 1.8MHz, V IN = 48V, V o = 1.3V, I o = 50A Resonant drivers for SRs V IN + HB 1 HB 2 LRLR N:1 CACA CBCB C2C2 C1C1 L F1 L F2 Q2Q2 Q1Q1 + VOVO i F2 CFCF RLRL i F1 iRiR + + TRTR V GS_Q1 V GS_Q2 V C1 V C2

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37 VRM Prototype 4 IRF7836 SR MOSFETs (Q g = 18-27nC @V GS = 4.5V, R g = 1 )

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38 Experimental Waveforms: DR1 V GS1 [2V/div] V GS2 [2V/div] DR1 measured waveforms driving 4 IRF7836 SR MOSFETs (no energy recovery) P loss = 1W each HB 1 HB 2

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39 References 1.D. Maksimovic, A MOS gate drive with resonant transitions, in Proc. Power Electron. Spec. Conf., 1991, pp. 527–532. 2.Y. Ren, M. Xu, Y. Meng, F. C. Lee, 12V VR Efficiency Improvement based on Two-stage Approach and a Novel Gate Driver, IEEE Power Electronics Specialists Conf. (PESC), June 2003, pp.2635-2641. 3.T. Lopez, G. Sauerlaender, T. Duerbaum, T. Tolle, A Detailed Analysis of a Resonant Gate Driver for PWM Applications, IEEE Applied Power Electronics Conf. (APEC), 2003, pp. 873-878. 4.K. Xu, Y. F. Liu and P. C. Sen, A New Resonant Gate Drive Circuit with Centre-Tapped Transformer, IECON, 2005, pp. 639-644. 5.Z. Yang, S. Ye and Y. F. Liu, A New Dual Channel Resonant Gate Drive Circuit for Synchronous Rectifiers, IEEE Applied Power Electronics Conf. (APEC), 2006, pp. 756-762. 6.Z. Zhang, Z. Yang, S. Ye, Y. F. Liu, Topology and Analysis of a New Resonant Gate Driver, IEEE Power Electronics Specialists Conf. (PESC), June 2006, pp. 1453-1459. 7.W. A. Tabisz, P. Gradzki, and F. C. Lee, Zero-voltage-switched quasi-resonant buck and flyback converters experimental results at 10 MHz,IEEE Power Electronics Specialists Conf. (PESC), 1987, pp. 404–413. 8.S. H. Weinberg, A novel lossless resonant MOSFET driver, IEEE Power Electronics Specialist Conf. (PESC), 1992, pp. 1003–1010. 9.H. L. N. Wiegman, A resonant pulse gate drive for high frequency applications, IEEE Applied Power Electronics Conf. (APEC), 1992, pp. 738–743. 10.Y. Panov and M. Jovanovic, Design considerations for 12-V/1.5-V, 50-A voltage regulator modules, IEEE Transactions. on Power Electronics, Vol.16, N°6, Nov. 2001, pp. 776-783. 11.Y. Chen, F. C. Lee, L. Amoroso, H. P. Wu, A resonant MOSFET Gate Driver with Efficient Energy Recovery, IEEE Transactions on Power Electronics, Vol. 19, NO. 2, March 2004, pp.470-477. 12.S. Pan, P. K. Jain, A New Pulse Resonant MOSFET Gate Driver with Efficient Energy Recovery, IEEE Power Electronics Specialists Conf. (PESC), June 2006. 13.W. Eberle, P. C. Sen and Y. F. Liu, A New Resonant Gate Drive Circuit with Efficient Energy Recovery and Low Conduction Loss, IECON, 2005, pp. 650-655. 14.W. Eberle, Y. F. Liu and P. C. Sen, A novel High Performance Resonant Gate Drive Circuit with Low Circulating Current, IEEE Applied Power Electronics Conf. (APEC), 2006, pp.324-330. 15.K.Yao, F. C. Lee, A Novel Resonant Gate Driver for High Frequency Synchronous Buck Converters, IEEE Transactions on Power Electronics, Vol. 17, No. 2, March 2002, pp. 180-186. 16.I. D. de Vries, A resonant power MOSFET/IGBT gate driver,IEEE Applied Power Electronics Conf. (APEC), 2002, pp. 179–185. 17.J. T. Strydom, M. A. de Rooij, J. D. van Wyk, A Comparison of Fundamental Gate-Driver Topologies for High Frequency Applications, IEEE Applied Power Electronics Conf. (APEC), 2004. 18.L. Huber, K. Hsu, M. Jovanovic, 1.8 MHz, 48 V Resonant VRM, IEEE Tran. on Power Electronics, Vol.1, N°1, Jan. 2006, pp. 79-88.

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