Presentation on theme: "An Introduction to Starburst Technologies, Inc. for DoD DMSMS Teaming Group by Richard S. Lowry."— Presentation transcript:
An Introduction to Starburst Technologies, Inc. for DoD DMSMS Teaming Group by Richard S. Lowry
Agenda u Introduction to Starburst Technologies, Inc. A brief discussion about our facility, our equipment and tools, our people, and our experience. u VHDL A short discussion on VHDL. Panacea to re- engineering???? u Increasing Challenges in Dealing with Obsolescence Future Challenges Future Solutions
About Us u Incorporated in October 1992 u We are a Woman-Owned Business u Internationally recognized ASIC design firm u Finest Engineering staff in the World –100+ years design experience –100+ ASIC designs –50+ design conversions u Offices located in Orlando, Florida
Our Facility u We lease 3,700 Sq. Ft. of Office Space. u The space includes: 10 Offices 3 Design Centers with 15 design seats Multi-media Conference Room ReceptionLibrary Break/Lunch Room
STIs Design Center u Ultra30, Ultra2, Sparc, and NT workstations u FTP site with T1 connection to Internet u State-of-the-art Design Software Available Model Tech System V simulator Renoir High-level design tools Leonardo Spectrum synthesis LSI Logics Toolkit, CMDE, FlexStream, Vega TeraForm RTL Place and Route DFT Advisor, BSD Architect, and FastScan Verilog -XL
We Have Extensive ASIC- Related Tool Experience u We have experience in most ASIC tools. Verilog-XL VCS Verilog-NC Quicksim ModelSim Design Compiler MOTIVE Leonardo Spectrum AMBIT Build Gates PrimeTime Test Compiler FastScan DFT Advisor PKS Formality Renoir Visual HDL BestBench TeraForm Verilog-XL VCS Verilog-NC Quicksim ModelSim Design Compiler MOTIVE Leonardo Spectrum AMBIT Build Gates PrimeTime Test Compiler FastScan DFT Advisor PKS Formality Renoir Visual HDL BestBench TeraForm
Services Provided u Turn Key ASIC and FPGA Design u Test Bench Development u Design Verification u Design Conversions u Verilog Training u On-Site Design Consulting u Design Center Services u Core Development u Design Tool and Methodology Consulting
We Have a Strong Customer Base Ericsson Smiths Industries Ericsson Smiths Industries AMIHoneywell/AlliedSignal AMIHoneywell/AlliedSignal LSI LogicSchwartz Electro Optics LSI LogicSchwartz Electro Optics Lucent TechnologiesDPT/ADAPTEC Lucent TechnologiesDPT/ADAPTEC Lockheed MartinRaytheon Lockheed MartinRaytheon Theseus LogicSynova, Inc. Theseus LogicSynova, Inc. Esperan, Ltd.Harris Esperan, Ltd.Harris Metric Systems Cadence Design Systems Metric Systems Cadence Design Systems
We Have Design Experience in Many Technologies u AT&T BELL LABS - NAVY NTDS chip u LOCKHEED MARTIN – GAPP Image Proc. ASICs u LOCKHEED MARTIN – RADAR Sig. Proc. ASICs u LUCENT - GIGABIT Ethernet / PCI Chip u APPLE COMPUTER - 3 Graphics Chips - PCI u ERICSSON - Telecom Network Switch ASICs u ERICSSON - Wireless Internet ASICs
We Have Design Experience (Contd) u XLNT - Gigabit Ethernet Chip u SYMBOL TECHNOLOGIES - Bar Code Decoder u SYNOVA - Rad Hard MIPS Processor u BROCADE - Router on a chip - RAMBUS & serial links u DPT - Data Path Chip – PCI u Igt – ATM ASIC
We Have Extensive ASIC- Related Tool Experience u We have experience with several ASIC Vendor tools and design flows. AMI CHIP EXPRESS AMI CHIP EXPRESS HONEYWELL LSI LOGIC HONEYWELL LSI LOGIC LUCENT TI LUCENT TI
ASIC-Related Language Experience u We employ industry standard languages in our day-to-day operations. u We are proficient with both Verilog and VHDL –Verilog is our primary HDL for design –We use VHDL as required. u We employ C/C++ as scripting and modeling languages.
We Have Conducted All Types of Design Conversions u FPGA to Gate Array 18 u LSI Gate Array to FPGA 6 u LSI Gate Array to AMI ASIC 30 u LSI Gate Array to Other ASIC 6 u LSI MIPS Core to HW RADHARD 2 u LSI DSP chip to LSI RADHARD 2 u VLSI Std Cell to LSI Std Cell 4
Design Conversions u We have converted designs from 1,500 to 150,000 gates. u Completely regenerated a design from schematics. u Have reengineered several proprietary megafunctions. u StarBlocks
StarBlocks u Starburst Technologies is in the process of developing a comprehensive set of synthesizable functions. Some of the functions that are currently available are: 3 port adders fast adders twos compliment multipliers Reed-Solomon Decoder UARTsFIFOs
VHSIC Hardware Description Language (VHDL) u Developed as a procurement specification. u Evolved into a Synthesis and Simulation language. u Different levels of abstraction available. –Behavioral – Simulation Only –RTL – Simulation and Synthesis –Gate – Simulation
Behavioral VHDL u Only describes the functionality of the design. A + B = C Used for definition and debug of design requirements and For definitions within testbenches Extensive engineering effort required to reproduce a complete design from a Behavioral model.
Register Transfer Language (RTL) VHDL u Describes the functionality and architecture of a design. u RTL is the input to Synthesis tools. u Additional information is required to duplicate design: –Synthesis Constraints –Timing Constraints Some engineering effort required to reproduce a Complete design from a RTL description.
Gate-Level VHDL u Describes the design as related to a particular Manufacturers gate-level library. u Also tied to a particular process. u May not provide a complete description for conversion: –Proprietary Megafunctions –Memory Elements –FPGA With the exception of missing elements, requires the least amount engineering effort to reproduce a complete design.
Increasing Challenges in Dealing with Obsolescence
Future Challenges u Designs are getting bigger. –1,000,000+ gates –Embedded IP u.5 micron lines are shutting down u Design documentation typically not available. –Misplaced netlists –No baseline simulations u DSM timing closure
Future Solutions u First we must instill a discipline in our engineers and managers to: Design for Reuse Reuse Methodology Manual, Keating and Bricaud. Kluwer Academic Publishers, 1998 Document and Properly Archive Designs
Solutions for Today u Each design must be evaluated separately. u When chip re-engineering is required: –Use as much of the original design database as possible. –Understand what pieces to the puzzle are missing and what it will take to regenerate these pieces. –Understand the pitfalls of using the newer manufacturing technology. DSM designs will inevitably have timing closure issues.
Solutions for Today u Remember that no set of simulation vectors can provide 100% verification of the conversion. u Static Timing Analysis and Formal Verification techniques should be used wherever possible.