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– 1 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Switched-Capacitor Circuits.

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Presentation on theme: "– 1 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Switched-Capacitor Circuits."— Presentation transcript:

1 – 1 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Switched-Capacitor Circuits

2 Continuous-Time Integrator – 2 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Goal: Approach: emulating resistors with switched capacitors

3 Concept of Switched Capacitor – 3 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 A switched capacitor is a discrete-time resistor RC time constant set by capacitor ratio C 2 /C 1 (match considerably better than R and C) and clock period T (flexibility) so, Non-overlapping two-phase clock

4 Switched Capacitors – 4 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Shunt- and series-type SCs are simple and cheap to implement Stray-insensitive SC requires 2 more switches, whats the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)? 2-phase clockSeries-typeShunt-type Stray-insensitive

5 Discrete-Time Integrator (DTI) – 5 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall phase clock Series-typeShunt-type What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present?

6 Shunt-Type DTI – 6 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Ф1 (sample) Charge conservation law (ideal): Total charge on C 1 and C 2 during Ф 1 Ф 2 transition must remain unchanged! Ф2 (update)

7 Shunt-Type DTI – 7 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Ф1 (sample) Ф2 (update)

8 Series-Type DTI – 8 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Ф1 (sample/update) Ф2 (reset C 1 ) VTF:

9 Stray Capacitance – 9 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Series-typeShunt-type Strays derive from D/S diodes and wiring capacitance VTF is modified due to strays Strays at the summing node is of no significance (virtual ground)

10 Stray-Insensitive SC Integrator – 10 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 VTF: Capacitors can be significantly sized down to save power/area Sizes are eventually limited by kT/C noise, mismatch, etc. InvertingNon-inverting VTF:

11 SC Amplifier – 11 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Non-integrating, memoryless (less the delay) Used in many applications of parametric amplification VTF:

12 – 12 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 SC Applications

13 CT Filter – 13 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 RLC prototype Active-RC Tow-Thomas CT biquad

14 SC DT Filter – 14 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 SC DT biquad Active-RC Tow-Thomas CT biquad

15 Sigma-Delta (ΣΔ) Modulator – 15 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

16 Pipelined ADC – 16 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

17 SC Common-Mode Feedback – 17 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough.

18 SC Common-Mode Feedback – 18 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012

19 – 19 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Noise in SC Circuits

20 Noise of CT Integrator – 20 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Noise in CT circuits can be simulated with SPICE (.noise)

21 Noise of SC Integrator – 21 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 SC circuits are NOT noise-free! Switches and op-amps introduce noise.

22 Sampling (Ф 1 ) Ideal Voltage Source – 22 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Noise is indistinguishable from signal after sampling The noise acquired by C 1 will be amplified in Ф 2 just like signal

23 Integration (Ф 2 ) – 23 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 No simulator can directly simulate the aggregated output noise!

24 Sampling (Ф 1 ) Noise – Cascaded Stages – 24 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering). But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking).

25 Sampled Noise Spectrum – 25 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Total integrated noise power remains constant SNR remains constant CT DT

26 – 26 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Nonideal Effects in SC Circuits

27 – 27 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.) –PP, MIM, and MOM are linear up to bits (nonlinear voltage coefficients negligible for most applications) –Gate caps are typically good for up to 8-10 bits Switches (MOS transistors) –Nonzero on-resistance (voltage dependent) –(Nonlinear) stray capacitance added (C gs, C gd, C gb, C db, C sb ) –Switch-induced sampling errors (charge injection, clock feedthrough, junction leakage, drain-source leakage, and gate leakage) Operational amplifiers –Offset –Finite-gain effects (voltage dependent) –Finite bandwidth and slew rate (measured by settling speed)

28 – 28 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Nonideal Effects of Switches

29 Nonzero On-Resistance – 29 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 FET channel resistance (thus tracking bandwidth) depends on signal level Usually (R on C S ) -1 (3-5)·ω -3dB of closed-loop op-amp for settling purpose

30 Clock Bootstrapping – 30 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Small on-resistance leads to large switches large parasitic caps and large clock buffers Clock bootstrapping keeps V GS of the switch constant constant on- resistance (body effect?) and less parasitics w/o the PMOS CMOSBootstrapped NMOS

31 Simplified Clock Bootstrapper – 31 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Pros Linearity Bandwidth Cons Device reliability Complexity

32 Switch-Induced Errors – 32 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Channel charge injection and clock feedthrough (on drain side) result in charge trapped on C S after switch is turned off. Clock feedthrough Charge injection

33 Clock Feedthrough and Charge Injection – 33 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Both phenomena sensitive to Z i, C S, and clock rise/fall time Offset, gain error, and nonlinearity introduced to the sampling Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models

34 Clock Rise/Fall-Time Dependence – 34 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Clock feedthroughCharge injection Fast turn-off Slow turn-off

35 Dummy Switch – 35 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Difficult to achieve precise cancellation due to the nonlinear dependence of ΔV on Z i, C S, and clock rise/fall time Sensitive to the phase alignment between Ф and Ф_

36 CMOS Switch – 36 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Very sensitive to phase alignment between Ф and Ф_ Subject to threshold mismatch between PMOS and NMOS Exact cancellation occurs only for one specific V in (which one?) Same size for P and N FETs

37 Differential Signaling – 37 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Signal-independent errors (offset) and even-order distortions cancelled Gain error and odd-order nonlinearities remain Balanced diff. input

38 Switch Performance – 38 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Charge injection: Bandwidth: Performance FoM: Technology scaling improves switch performance! On-resistance:

39 Leakage in SC Circuits – 39 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 I1 – diode leakage (existing in the old days too) I2 – sub-threshold drain-source leakage of summing-node switch I3 – gate leakage (FN tunneling) of amplifier input transistors Leakage currents are highly temperature- and process-dependent; the lower limit of clock frequency is often determined by leakage Φ 1 = high, Φ 2 = low

40 DS Leakage – 40 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall μm CMOS A 0 = G m ·R o = 90dB R o 2MΩ R leak 0.6V/3μA 0.2MΩ A 0 = G m ·(R leak //R o ) 70dB

41 Gate Leakage – 41 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Direct tunneling through the thin gate oxide Short-channel MOSFET behaves increasingly like BJTs Violates the high-impedance assumption of the summing node

42 Switch Size Optimization – 42 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 To minimize switch-induced error voltages, small transistor size, slow turn-off, low source impedance should be used. For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well. Guidelines Always use minimum channel length for switches as long as leakage allows. For a given speed, switch sizes can be optimized w/ simulation. Be aware of the limitations of simulators (SPICE etc.) usinglumped device models.

43 – 43 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Nonideal Effects of Op-Amps

44 – 44 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed)

45 Offset Voltage – 45 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 V i = 0

46 Autozeroing – 46 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Also eliminates low-frequency noise, e.g., 1/f noise A.k.a. correlated double sampling (CDS)

47 Chopper Stabilization – 47 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, A low-noise chopper-stabilized differential switched-capacitor filtering technique, IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp , 1981.

48 Chopper Stabilization – 48 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Also eliminates DC offset voltage of A 1

49 Chopper-Stabilized Differential Op-Amp – 49 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Integrators/amplifiers can be built using these op-amps Some oversampling is useful to facilitate the implementation

50 Ideal SC Amplifier – 50 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Closed-loop gain is determined by the capacitor ratio by design But this is assuming X is an ideal summing node (the op-amp is ideal)

51 Finite-Gain Effect in SC Amplifier – 51 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012

52 – 52 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Practical Issues

53 Analog vs. Digital Supply Lines – 53 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Sharing sensitive analog supplies with digital ones is a very bad idea.

54 Analog vs. Digital Supply Lines – 54 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Dedicated pads for analog and digital supplies On-chip bypass capacitors help (watch ringing) Off-chip chokes (large inductors) can stop noise propagation at board level

55 Supply Capacitance – 55 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Any summing-node stray capacitance can be a potential coupling path. V DD, V SS, substrate, clock line, and digital noises, body effect, etc. Fully differential circuits help to reject common-mode noise and coupling.

56 Supply Capacitance – 56 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Avoid connecting bottom-plate parasitics to the summing node Avoid crossing other signal lines with the summing node Shielding can mitigate substrate noise coupling

57 Clock Generation – 57 – Data ConvertersSwitched-Capacitor CircuitsProfessor Y. Chiu EECT 7327Fall 2012 Clock-gated ring structure Non-overlapping time determined by inverter delays, sensitive to process, voltage, and temperature (PVT) variations DLL is an alternative, often used in high-speed designs


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