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**Switched-Capacitor Circuits**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Switched-Capacitor Circuits

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**Continuous-Time Integrator**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Continuous-Time Integrator Goal: Approach: emulating resistors with switched capacitors

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**Concept of Switched Capacitor**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Concept of Switched Capacitor Non-overlapping two-phase clock so, A switched capacitor is a discrete-time “resistor” RC time constant set by capacitor ratio C2/C1 (match considerably better than R and C) and clock period T (flexibility)

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Switched Capacitors Shunt-type Series-type 2-phase clock Stray-insensitive Shunt- and series-type SCs are simple and cheap to implement Stray-insensitive SC requires 2 more switches, what’s the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)?

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**Discrete-Time Integrator (DTI)**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Discrete-Time Integrator (DTI) Shunt-type Series-type 2-phase clock What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present?

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**Shunt-Type DTI Charge conservation law (ideal):**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Shunt-Type DTI Ф1 (sample) Ф2 (update) Charge conservation law (ideal): Total charge on C1 and C2 during Ф1→ Ф2 transition must remain unchanged!

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**Shunt-Type DTI Ф1 (sample) Ф2 (update)**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Shunt-Type DTI Ф1 (sample) Ф2 (update)

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**Series-Type DTI VTF: Ф1 (sample/update) Ф2 (reset C1)**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Series-Type DTI Ф1 (sample/update) Ф2 (reset C1) VTF:

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**Stray Capacitance Strays derive from D/S diodes and wiring capacitance**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Stray Capacitance Shunt-type Series-type Strays derive from D/S diodes and wiring capacitance VTF is modified due to strays Strays at the summing node is of no significance (virtual ground)

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**Stray-Insensitive SC Integrator**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Stray-Insensitive SC Integrator “Inverting” “Non-inverting” VTF: VTF: Capacitors can be significantly sized down to save power/area Sizes are eventually limited by kT/C noise, mismatch, etc.

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**SC Amplifier VTF: Non-integrating, memoryless (less the delay)**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 SC Amplifier VTF: Non-integrating, memoryless (less the delay) Used in many applications of parametric amplification

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 SC Applications

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**CT Filter RLC prototype Active-RC Tow-Thomas CT biquad**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 CT Filter RLC prototype Active-RC Tow-Thomas CT biquad

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**SC DT Filter Active-RC Tow-Thomas CT biquad SC DT biquad**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 SC DT Filter Active-RC Tow-Thomas CT biquad SC DT biquad

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**Sigma-Delta (ΣΔ) Modulator**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Sigma-Delta (ΣΔ) Modulator DTI + 1-bit comparator + 1-bit DAC = first-order ΣΔ ADC

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**SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Pipelined ADC SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC

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**SC Common-Mode Feedback**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 SC Common-Mode Feedback CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough.

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**SC Common-Mode Feedback**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 SC Common-Mode Feedback

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Noise in SC Circuits

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**Noise in CT circuits can be simulated with SPICE (.noise)**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Noise of CT Integrator Noise in CT circuits can be simulated with SPICE (.noise)

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**SC circuits are NOT noise-free! Switches and op-amps introduce noise.**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Noise of SC Integrator SC circuits are NOT noise-free! Switches and op-amps introduce noise.

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**Sampling (Ф1) Ideal Voltage Source**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Sampling (Ф1) Ideal Voltage Source Noise is indistinguishable from signal after sampling The noise acquired by C1 will be amplified in Ф2 just like signal

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**No simulator can directly simulate the aggregated output noise!**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Integration (Ф2) No simulator can directly simulate the aggregated output noise!

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**Sampling (Ф1) Noise – Cascaded Stages**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Sampling (Ф1) Noise – Cascaded Stages Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering). But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking).

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**Sampled Noise Spectrum**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Sampled Noise Spectrum CT DT Total integrated noise power remains constant SNR remains constant

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**Nonideal Effects in SC Circuits**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonideal Effects in SC Circuits

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**Nonideal Effects in SC Circuits**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonideal Effects in SC Circuits Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.) PP, MIM, and MOM are linear up to bits (nonlinear voltage coefficients negligible for most applications) Gate caps are typically good for up to 8-10 bits Switches (MOS transistors) Nonzero on-resistance (voltage dependent) (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb) Switch-induced sampling errors (charge injection, clock feedthrough, junction leakage, drain-source leakage, and gate leakage) Operational amplifiers Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed)

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**Nonideal Effects of Switches**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonideal Effects of Switches

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**Nonzero On-Resistance**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonzero On-Resistance FET channel resistance (thus tracking bandwidth) depends on signal level Usually (RonCS)-1 ≥ (3-5)·ω-3dB of closed-loop op-amp for settling purpose

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**Clock Bootstrapping CMOS Bootstrapped NMOS**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Clock Bootstrapping CMOS Bootstrapped NMOS Small on-resistance leads to large switches → large parasitic caps and large clock buffers Clock bootstrapping keeps VGS of the switch constant → constant on-resistance (body effect?) and less parasitics w/o the PMOS

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**Simplified Clock Bootstrapper**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Simplified Clock Bootstrapper Pros Linearity Bandwidth Cons Device reliability Complexity

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**Switch-Induced Errors**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Switch-Induced Errors Clock feedthrough Charge injection Channel charge injection and clock feedthrough (on drain side) result in charge trapped on CS after switch is turned off.

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**Clock Feedthrough and Charge Injection**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Clock Feedthrough and Charge Injection Both phenomena sensitive to Zi, CS, and clock rise/fall time Offset, gain error, and nonlinearity introduced to the sampling Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models

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**Clock Rise/Fall-Time Dependence**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Clock Rise/Fall-Time Dependence Clock feedthrough Charge injection Fast turn-off Slow turn-off

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Dummy Switch Difficult to achieve precise cancellation due to the nonlinear dependence of ΔV on Zi, CS, and clock rise/fall time Sensitive to the phase alignment between Ф and Ф_

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**CMOS Switch Same size for P and N FETs**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 CMOS Switch Same size for P and N FETs Very sensitive to phase alignment between Ф and Ф_ Subject to threshold mismatch between PMOS and NMOS Exact cancellation occurs only for one specific Vin (which one?)

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**Differential Signaling**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Differential Signaling Balanced diff. input Signal-independent errors (offset) and even-order distortions cancelled Gain error and odd-order nonlinearities remain

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**Technology scaling improves switch performance!**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Switch Performance On-resistance: Bandwidth: Charge injection: Performance FoM: Technology scaling improves switch performance!

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**Leakage in SC Circuits Φ1 = “high”, Φ2 = “low”**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Leakage in SC Circuits Φ1 = “high”, Φ2 = “low” I1 – diode leakage (existing in the old days too) I2 – sub-threshold drain-source leakage of summing-node switch I3 – gate leakage (FN tunneling) of amplifier input transistors Leakage currents are highly temperature- and process-dependent; the lower limit of clock frequency is often determined by leakage

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**DS Leakage 0.13-μm CMOS A0 = Gm·Ro = 90dB Ro ≈ 2MΩ Rleak ≈ 0.6V/3μA**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 DS Leakage 0.13-μm CMOS A0 = Gm·Ro = 90dB Ro ≈ 2MΩ Rleak ≈ 0.6V/3μA ≈ 0.2MΩ A0 = Gm·(Rleak//Ro) ≈ 70dB

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**Gate Leakage Direct tunneling through the thin gate oxide**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Gate Leakage Direct tunneling through the thin gate oxide Short-channel MOSFET behaves increasingly like BJT’s Violates the high-impedance assumption of the summing node

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**Switch Size Optimization**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Switch Size Optimization To minimize switch-induced error voltages, small transistor size, slow turn-off, low source impedance should be used. For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well. Guidelines Always use minimum channel length for switches as long as leakage allows. For a given speed, switch sizes can be optimized w/ simulation. Be aware of the limitations of simulators (SPICE etc.) using lumped device models.

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**Nonideal Effects of Op-Amps**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonideal Effects of Op-Amps

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**Nonideal Effects of Op-Amps**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Nonideal Effects of Op-Amps Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed)

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Offset Voltage Vi = 0

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**Autozeroing Also eliminates low-frequency noise, e.g., 1/f noise**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Autozeroing Also eliminates low-frequency noise, e.g., 1/f noise A.k.a. correlated double sampling (CDS)

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**Chopper Stabilization**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Chopper Stabilization Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, “A low-noise chopper-stabilized differential switched-capacitor filtering technique,” IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp , 1981.

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**Chopper Stabilization**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Chopper Stabilization Also eliminates DC offset voltage of A1

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**Chopper-Stabilized Differential Op-Amp**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Chopper-Stabilized Differential Op-Amp Integrators/amplifiers can be built using these op-amps Some oversampling is useful to facilitate the implementation

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Ideal SC Amplifier Closed-loop gain is determined by the capacitor ratio by design But this is assuming X is an ideal summing node (the op-amp is ideal)

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**Finite-Gain Effect in SC Amplifier**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Finite-Gain Effect in SC Amplifier

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 Practical Issues

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**Analog vs. Digital Supply Lines**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Analog vs. Digital Supply Lines Sharing sensitive analog supplies with digital ones is a very bad idea.

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**Analog vs. Digital Supply Lines**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Analog vs. Digital Supply Lines Dedicated pads for analog and digital supplies On-chip bypass capacitors help (watch ringing) Off-chip chokes (large inductors) can stop noise propagation at board level

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 “Supply” Capacitance Any summing-node stray capacitance can be a potential coupling path. VDD, VSS, substrate, clock line, and digital noises, body effect, etc. Fully differential circuits help to reject common-mode noise and coupling.

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**Data Converters Switched-Capacitor Circuits Professor Y. Chiu**

EECT Fall 2012 “Supply” Capacitance Avoid connecting bottom-plate parasitics to the summing node Avoid crossing other signal lines with the summing node Shielding can mitigate substrate noise coupling

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**Clock Generation Clock-gated ring structure**

Data Converters Switched-Capacitor Circuits Professor Y. Chiu EECT Fall 2012 Clock Generation Clock-gated ring structure Non-overlapping time determined by inverter delays, sensitive to process, voltage, and temperature (PVT) variations DLL is an alternative, often used in high-speed designs

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