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Created by Steven Chambers in Fall 2012

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1 Created by Steven Chambers in Fall 2012
ECE 311 – Electronics Lab I Pre-labs for ECE 311 Created by Steven Chambers in Fall 2012 Last Updated: 12/20/2012

2 Laboratory 0 – Laboratory Demonstration

3 Introduction to Laboratory 0
Curve Tracer Plots I-V curve for two and three terminal devices Can plot a family of curves for different bias conditions Used in this lab to give characteristics of diodes and transistors Current/Voltage/Power limitations used to prevent destruction of device under test (DUT)

4 Background Information
Bipolar Junction Transistor (BJT) Three terminal device (Emitter, Base, Collector) Base current controls Collector-Emitter current I-V curve Y-axis: IC X-axis: VCE Family of curves represents different IB values As IB increases, IC increases for the same VCE value

5 Contact Information Instructor: Name: Office: Phone: Office Hours: As needed ( for appointment) Lab Coordinator: Name: Dr. Timothy Burg Office: 307 Fluor Daniel (EIB) Phone: (864)

6 Mandatory Safety Video
Have your students watch the attached safety video.

7 Preparations for Next Week
B2SPICE Circuit simulation software Uses computer models to predict circuit behavior All parts used are considered ideal Observed value will differ from simulated value, but still good estimation Tests most often used in this lab are DC Sweep, Transient testing, and frequency sweep DC Sweep used for both simulations of next weeks lab

8 Preparations for Next Week
For Part 2: Click Sweeps tab under DC Sweep Then click Set up Sweeps The dialogue to the right will appear. Use these settings to properly sweep the R from 100 to 1000 to 10k ohms.

9 Laboratory 1 – Diode Characteristic

10 Introduction to Lab 1 Diode – Allows current to flow in one direction under forward bias rd – dynamic forward resistance rd = ΔVD/ ΔID (reciprocal of I-V slope) RD – static forward resistance RD = VD/ID Vγ – cut-in voltage point where appreciable current conduction begins n – ideality factor dependent upon physical characteristics of diodes VBR – breakdown voltage IS – reverse saturation current current that flows under reverse bias VT – thermal voltage = V at room temperature VD ID

11 Diode Characteristic Part 1A will replicate forward bias on curve tracer Part 1B will replicate reverse bias on a Zener diode Zener diodes have a lower VBR because they are designed to keep a constant voltage drop across it

12 Ideality Factor “The ideality factor, n, depends on the type of semiconductor material used in the diode, the manufacturing process, the forward voltage, and the temperature.” Its value generally varies between 1 and 2. For voltages less than about 0.5 V, n ~ 2; for higher voltages, n ~ 1. (experiment shows values typically 1.15 ≤ n ≤ 1.2) The ideality factor, n, can readily be found by plotting the diode forward current on a logarithmic axis vs. the diode voltage on a linear axis.

13 Finding Ideality factor, n
Pick two points where currents are 10 times different Find ∆ 𝑉 𝐷 = ? ∆ 𝑉 𝐷 𝑛 𝑉 𝑇 = ln 10 =2.3 𝑉 𝑇 = 𝑉 ∆ 𝑉 𝐷 =2.3×𝑛× 𝑉 𝑇 ∆ 𝑉 𝐷 =2.3×𝑛× 𝑉 𝑇 =2.3×𝑛×0.0258= 𝑛=𝑛×59.3 𝑚𝑉 𝒏= ∆ 𝑽 𝑫 𝟓𝟗.𝟑𝒎𝑽

14 Cut-in Voltage Vγ: 0.4V to 0.7V for silicon 0.2V to 0.4V for germanium
“If the applied voltage exceeds Vγ, the diode current increases rapidly.”

15 Three diode resistances are commonly calculated:
DC or Static forward resistance, RF or RD AC or Dynamic forward resistance, rf or rd Reverse resistance, rr the reciprocal of the slope of the reverse characteristic, prior to breakdown Applying the diode equation and differentiating

16 Junction Capacitance of Diode ( Cj )

17 Experiment: Measurement of diode characteristics
Forward I-V Characteristic Use the curve tracer to obtain the forward characteristics of the silicon 1N4004 diode. follow the steps mentioned in lab manual for selecting Vmax =2V, Imax = 2mA and Pmax =0.4W Fill out table 1.1 and perform calculations to find RF and rd

18 Reverse I-V Characteristic
Use Zener diode (this one looks transparent) Note the reverse breakdown voltage (around -14.6V)

19 SIMPLE DIODE CIRCUIT Build the circuit Measure the output voltage, V0
Vary the Vin from 0V to 5V for R= 100Ω change R = 1k Ω and 10k Ω Fill out table 1.2

20 Preparations for Next Lab
Post Lab 1 All questions under Lab Report section (Part 1 and Part 2) should be answered Pre Lab 2 Figures 2.3 and 2.5 will be simulated Use a sinusoidal voltage source set to 60 Hz and 4 volt amplitude (8 V peak to peak) Run transient test for 4 periods (f = 60 Hz T = 1/f start time = 0)

21 Laboratory 2 – Power Supply operation

22 Half-wave Rectifier Diode forward biased for Vin > Vγ Diode reverse biased for Vin < Vγ Allows current to conduct for roughly half of AC cycle Vm = Vp - Vγ

23 Full-wave Rectifier D2 and D3 forward biased when Vin > 2Vγ
Vm = Vp – 2Vγ Output frequency is twice that of input Output does not share common ground with input

24 Filtering Adding a capacitor in parallel with load resistor creates a filter Capacitor will charge up on first half of cycle then discharge slowly based on capacitance This creates a voltage source with ripple Vr = Vm – Vmin

25 Preparations for Next Lab
Post Lab 2 3 questions under Lab Report Pre Lab 3 – First Design Lab I will split the class. Half the class will come for the first hour. Other half will come for the second. Bring your design calculations with you to lab Please print ECE 311 – Lab 3 Lab Summary page from lab manual and bring with you to next lab. This will be turned in as your post lab prior to leaving lab next week.

26 Laboratory 3 – Power Supply Design

27 Power Supply Design Calculations
This lab is to be completed individually Remember Vin is measured after the source resistor Rs Fill out Lab Summary sheet and turn in before your leave

28 Preparations for Next Lab
Pre Lab 4 Simulate circuits 4.5(a) (Vb = 0 and 2 V), 4.6(a) (Vb = 0 and 2 V), 4.7, and 4.8 There is an error in the prelab statement. DO NOT SIMULATE FIGURE 4.4(a). Lab Report: You are to complete a formal lab report on your choice of Lab 1-3. You have 2 weeks to complete the report. It is to be submitted electronically before 5 PM on 10/9. Follow report format in the lab manual and look to the rubric uploaded on blackboard to see how it will be graded

29 Laboratory 4 – Diode Clippers and Clampers

30 Clipper Circuit that limits the output voltage to either an upper or lower limit (or both) through the use of diodes and voltage sources Diode begins conducting and holds output to a desired level (V + Vγ in the configuration seen below) Diode and battery orientation determine whether circuit is positive or negative clipper

31 Clamper Circuit that shifts the DC value of an input voltage through the use of a diode and capacitor Diode conducts on negative half cycle to allow capacitor to charge Once charged, capacitor passes AC signal shifted by the charge built on C Diode polarity determines positive or negative clamping (positive pictured below) RC time constant must be much larger than input signal period

32 Note on circuit connection
The NI-Elvis VPS is internally grounded This means no physical wire connection on your board is required to ground the voltage source For Vb = 0, connect diode straight to ground For non-zero Vb, connect diode to VPS supply + or supply - Connection already made within NI-Elvis board

33 Preparations for Next Lab
Post Lab 4 3 questions under Lab Report Pre Lab 5 Be familiar with BJT transistor operation and read through lab I do not require you to bring in graph paper Remember: Lab report due next week

34 Laboratory 5 – Bipolar Junction transistor characteristics

35 Bipolar Junction Transistor
Three terminal device: Collector, Emitter, Base Collect-Emitter current controlled by B-E current Four regions of operation {NPN (PNP)}: Cutoff – Both P-N Junctions reverse biased Saturation – Both P-N Junctions forward biased Forward Active – B-E (B-C) forward biased, B-C (B-E) reverse biased Inverse Active – B-E (B-C) reverse biased, B-C (B-E) forward biased N P N P N P

36 Output Characteristic
Forward Active Saturation Cutoff

37 Transistor Parameters
hFE = IC/IB = β – dc current gain hfe = ΔIC/ΔIB = βo – small signal (ac) current gain hie = ΔVBE/ΔIB = rπ – input resistance hoe = ΔIC/ΔVCE – output conductance hre = ΔVBE/ΔVCE – voltage feedback ratio hie can be approximated from βVT/ICQ VA – Early Voltage

38 Preparations for Next Lab
Post Lab 5 6 questions under Lab Report Pre Lab 6 Figure 6.2 DC Sweep to find Q point Figure 6.1 Transient analysis for various R Use transient setup given in pre lab Remember: Electronic copy of lab report due tonight by 5 pm

39 Laboratory 6 – BJT Common-emitter circuit bias

40 Common Emitter Bias Circuit
Emitter is used as a reference point for both input and output R1 and R2 form a bias network to set a desired base current RC used to set output voltage levels RE helps reduce circuit variation with β but also reduces AC voltage gain

41 Q-Point Bias circuit is used to select an operating (Q) point Q point should be well into the forward active region to get a properly behaving amplifier circuit When adding a small signal AC voltage, the output voltage will shift with the AC input based on gain If the Q point is too close to saturation or cutoff, output waveform will distort and circuit will not behave as a proper amplifier

42 Common Emitter Amplifier
AC input signal can be added to base terminal (C1 used to filter out any DC component) VO is takes from collector terminal to ground (C2 once again used to remove DC component) CE added to increase AC gain; Emitter is shorted to ground for AC – We will explore this more next week in Lab 7

43 Preparations for Next Lab
Post Lab 6 4 questions under Lab Report Pre Lab 7 Simulate circuit 7.1 for the 10 different configurations given in the lab manual

44 Laboratory 7 – BJT Common-emitter circuit voltage gain

45 Common Emitter Amplifier
Once Q point is established, small AC signal can be added to base This signal is amplified and seen at the collector terminal

46 Hybrid-π Equivalent Circuit
Used to model BJT response to small signal AC input gm = ICQ/VT Ro = VA/ICQ Rπ = β/gm When applied to overall circuit, can provide small signal voltage gain from input vs output transfer function

47 Effect of Emitter Capacitor
With CE: Without CE: With CE, two sides of circuit only share a common ground; without CE, RE adds a feedback loop which produces a voltage divider, reducing Vπ and the gain

48 Frequency Response Capacitors in this circuit have been selected so they essentially provide 0 impedance at circuit operating frequency. As frequency is changed, the capacitors start to produce an appreciable impedance; thus, lowering the gain of the circuit.

49 Preparations for Next Lab
Post Lab 7 4 Questions under Lab Report Pre Lab 8 2 Hour group design lab – Each student should read through and do design calculations individually and perform simulations Lab Report 2: Due 11/13 by 5:00 PM, electronic submission Pick from Labs 4-7

50 Laboratory 8 – bjt common emitter design I

51 Mesh analysis provides Av
Equivalent Circuit RO ignored Mesh analysis provides Av Design Calculations: β = 200 hib + RE = 235 Ω IBQ = µA Rac = 2.585k Ω hie = 3.91k Ω Rdc = 4.935k Ω hib = Ω ICQ = 1.33 mA RE = 215 Ω VCEQ = V R2 = 4.785k Ω VBB = V R1 = k Ω

52 Preparations for Next Lab
Post Lab 8: 2 Questions under Lab Report Do not do a full report for question 1. Simply provide me the design calculations, results, and comparison. Pre Lab 9: Individual Design Lab Bring calculations with you to next lab Print Lab Summary to turn in as Post Lab 9

53 Laboratory 9 – BJT common emitter design II

54 Equivalent Circuit Ro ignored Mesh analysis Vπ = Vs Vo = -(RC//RL)gmVπ Av = -(RC//RL)gm gm = ICQ/VT When RC = RL, Av = -RCICQ/2VT

55 Design Calculations Rac = 2.35k Ω R2 = 28.26k Ω ICQ = mA R1 = 97.92k Ω VCEQ = 3V VBB = V β = 200 IBQ = A hie = 4.073k Ω hib = Ω Rdc = 5.797k Ω RE = 1.097k Ω

56 Preparations for Next Lab
Post Lab 9 is to be turned in before you leave today Pre Lab 10 Read through the lab and be familiar with FET operation

57 Laboratory 10 – Field effect transistors

58 N-type channel with ohmic contacts at both ends
JFET Operation N-Channel JFET P-type gates N-type channel with ohmic contacts at both ends P-Channel switches doping type positions Current flow is controlled by gate bias VGS = 0 – Depletion regions exist between reverse biased p-n junctions, but a channel of n-type material allows current flow from drain to source VGS << 0 – Depletion region extends completely across n-type region cutting off current flow gate

59 JFET Equations Linear Region IDS = Kn [2(VGS – VP) VDS – VDS2] Where Kn = IDSS/VP2 IDSS – 0 Voltage current VP – pinchoff voltage Saturation Region IDS = Kn(VGS(Sat))2

60 Preparations for Next Lab
Post Lab 10 3 questions under Lab Report Pre Lab 11 Simulate Figure 11.6

61 Laboratory 11 – FET Bias and amplification

62 Similar circuit layout to BJT amplifier circuits
JFET Amplifier Similar circuit layout to BJT amplifier circuits Common-drain analogous to Common-emitter Common-source analogous to Common-collector Voltage controlled device with negligible current draw into gate Only reverse saturation current of p-n junctions will flow Common-source Common-drain

63 JFET Small Signal AC Model
gm = ΔID/ΔVGS rd = dVDS/dID Amplification μ = gmrd When applied to common-drain circuit: If RS = 0 or bypassed Av = gm(rd||RD)

64 Preparations for Next Lab
Post Lab 11 3 questions under Lab Report Pre Lab 12 Be familiar with logic gate operation Simulate both CMOS inverter and NAND gate

65 Laboratory 12 – basic logic circuits

66 CMOS Logic Complementary Metal Oxide Semiconductor (CMOS) Utilizes both pMOS and nMOS transistors Currently the most widely used technology for logic gates CMOS has helped push speeds faster and sizes smaller due to the ever improving transistor technology that allows lower voltage operation and smaller gate sizes

67 CMOS Inverter pMOS transistor source tied to VCC nMOS transistor source tied to GND Both gates tied together and used as input Both drains tied together and used as output When In = 5 V: pMOS off, nMOS on, Out grounded When In = 0 V: pMOS on, nMOS off, Out tied to +5

68 Slew Rate Slew rate refers to the rate at which signals rise and fall Rise and fall times determine how fast a circuit can operate (maximum operating frequency) Real signals do not instantaneously switch from high to low Transition times can lead to circuit glitches or missed data

69 The End! Enjoy the rest of your semester

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