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1 Clemson ECE Laboratories ECE 311 – Electronics Lab I Pre-labs for ECE 311 Created by Steven Chambers in Fall 2012 Last Updated: 12/20/2012.

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Presentation on theme: "1 Clemson ECE Laboratories ECE 311 – Electronics Lab I Pre-labs for ECE 311 Created by Steven Chambers in Fall 2012 Last Updated: 12/20/2012."— Presentation transcript:

1 1 Clemson ECE Laboratories ECE 311 – Electronics Lab I Pre-labs for ECE 311 Created by Steven Chambers in Fall 2012 Last Updated: 12/20/2012

2 2 Clemson ECE Laboratories LABORATORY 0 – LABORATORY DEMONSTRATION

3 3 Clemson ECE Laboratories Introduction to Laboratory 0 Curve Tracer – Plots I-V curve for two and three terminal devices – Can plot a family of curves for different bias conditions – Used in this lab to give characteristics of diodes and transistors – Current/Voltage/Power limitations used to prevent destruction of device under test (DUT)

4 4 Clemson ECE Laboratories Background Information Bipolar Junction Transistor (BJT) – Three terminal device (Emitter, Base, Collector) – Base current controls Collector-Emitter current – I-V curve Y-axis: I C X-axis: V CE Family of curves represents different I B values As I B increases, I C increases for the same V CE value

5 5 Clemson ECE Laboratories Contact Information Instructor: Name: Office: Phone: Office Hours: As needed ( for appointment) Lab Coordinator: Name: Dr. Timothy Burg Office: 307 Fluor Daniel (EIB) Phone: (864)

6 6 Clemson ECE Laboratories Mandatory Safety Video

7 7 Clemson ECE Laboratories Preparations for Next Week B2SPICE – Circuit simulation software – Uses computer models to predict circuit behavior – All parts used are considered ideal Observed value will differ from simulated value, but still good estimation – Tests most often used in this lab are DC Sweep, Transient testing, and frequency sweep – DC Sweep used for both simulations of next weeks lab

8 8 Clemson ECE Laboratories Preparations for Next Week For Part 2: Click Sweeps tab under DC Sweep Then click Set up Sweeps The dialogue to the right will appear. Use these settings to properly sweep the R from 100 to 1000 to 10k ohms.

9 9 Clemson ECE Laboratories LABORATORY 1 – DIODE CHARACTERISTIC

10 10 Clemson ECE Laboratories Introduction to Lab 1 Diode – Allows current to flow in one direction under forward bias r d – dynamic forward resistance r d = ΔV D / ΔI D (reciprocal of I-V slope) R D – static forward resistance R D = V D /I D V γ – cut-in voltage point where appreciable current conduction begins n – ideality factor dependent upon physical characteristics of diodes V BR – breakdown voltage I S – reverse saturation current current that flows under reverse bias V T – thermal voltage = V at room temperature IDID - V D +

11 11 Clemson ECE Laboratories Diode Characteristic Part 1A will replicate forward bias on curve tracer Part 1B will replicate reverse bias on a Zener diode – Zener diodes have a lower V BR because they are designed to keep a constant voltage drop across it

12 12 Clemson ECE Laboratories Ideality Factor The ideality factor, n, depends on the type of semiconductor material used in the diode, the manufacturing process, the forward voltage, and the temperature. (experiment shows values typically 1.15 n 1.2) Its value generally varies between 1 and 2. For voltages less than about 0.5 V, n ~ 2; for higher voltages, n ~ 1. (experiment shows values typically 1.15 n 1.2) The ideality factor, n, can readily be found by plotting the diode forward current on a logarithmic axis vs. the diode voltage on a linear axis.

13 13 Clemson ECE Laboratories Finding Ideality factor, n

14 14 Clemson ECE Laboratories Cut-in Voltage Vγ: 0.4V to 0.7V for silicon 0.2V to 0.4V for germanium If the applied voltage exceeds Vγ, the diode current increases rapidly.

15 15 Clemson ECE Laboratories Diode Resistance Three diode resistances are commonly calculated: DC or Static forward resistance, R F or R D AC or Dynamic forward resistance, r f or r d Reverse resistance, r r – the reciprocal of the slope of the reverse characteristic, prior to breakdown Applying the diode equation and differentiating

16 16 Clemson ECE Laboratories Junction Capacitance of Diode ( C j )

17 17 Clemson ECE Laboratories Experiment: Measurement of diode characteristics Forward I-V Characteristic – Use the curve tracer to obtain the forward characteristics of the silicon 1N4004 diode. – follow the steps mentioned in lab manual for selecting V max =2V, I max = 2mA and P max =0.4W – Fill out table 1.1 and perform calculations to find R F and r d

18 18 Clemson ECE Laboratories Reverse I-V Characteristic Use Zener diode (this one looks transparent) – Note the reverse breakdown voltage (around -14.6V)

19 19 Clemson ECE Laboratories SIMPLE DIODE CIRCUIT Build the circuit Measure the output voltage, V 0 Vary the V in from 0V to 5V for R= 100Ω change R = 1k Ω and 10k Ω Fill out table 1.2

20 20 Clemson ECE Laboratories Preparations for Next Lab Post Lab 1 – All questions under Lab Report section (Part 1 and Part 2) should be answered Pre Lab 2 – Figures 2.3 and 2.5 will be simulated – Use a sinusoidal voltage source set to 60 Hz and 4 volt amplitude (8 V peak to peak) – Run transient test for 4 periods (f = 60 Hz T = 1/f start time = 0)

21 21 Clemson ECE Laboratories LABORATORY 2 – POWER SUPPLY OPERATION

22 22 Clemson ECE Laboratories Half-wave Rectifier Diode forward biased for V in > V γ Diode reverse biased for V in < V γ Allows current to conduct for roughly half of AC cycle V m = V p - V γ

23 23 Clemson ECE Laboratories Full-wave Rectifier D2 and D3 forward biased when V in > 2V γ D1 and D4 forward biased when V in < 2V γ V m = V p – 2V γ Output frequency is twice that of input Output does not share common ground with input

24 24 Clemson ECE Laboratories Filtering Adding a capacitor in parallel with load resistor creates a filter Capacitor will charge up on first half of cycle then discharge slowly based on capacitance This creates a voltage source with ripple V r = V m – V min

25 25 Clemson ECE Laboratories Preparations for Next Lab Post Lab 2 – 3 questions under Lab Report Pre Lab 3 – First Design Lab – I will split the class. Half the class will come for the first hour. Other half will come for the second. – Bring your design calculations with you to lab – Please print ECE 311 – Lab 3 Lab Summary page from lab manual and bring with you to next lab. This will be turned in as your post lab prior to leaving lab next week.

26 26 Clemson ECE Laboratories LABORATORY 3 – POWER SUPPLY DESIGN

27 27 Clemson ECE Laboratories Power Supply Design Calculations This lab is to be completed individually Remember V in is measured after the source resistor R s Fill out Lab Summary sheet and turn in before your leave

28 28 Clemson ECE Laboratories Preparations for Next Lab Pre Lab 4 – Simulate circuits 4.5(a) (V b = 0 and 2 V), 4.6(a) (V b = 0 and 2 V), 4.7, and 4.8 – There is an error in the prelab statement. DO NOT SIMULATE FIGURE 4.4(a). Lab Report: You are to complete a formal lab report on your choice of Lab 1-3. You have 2 weeks to complete the report. It is to be submitted electronically before 5 PM on 10/9. – Follow report format in the lab manual and look to the rubric uploaded on blackboard to see how it will be graded

29 29 Clemson ECE Laboratories LABORATORY 4 – DIODE CLIPPERS AND CLAMPERS

30 30 Clemson ECE Laboratories Clipper Circuit that limits the output voltage to either an upper or lower limit (or both) through the use of diodes and voltage sources Diode begins conducting and holds output to a desired level (V + V γ in the configuration seen below) Diode and battery orientation determine whether circuit is positive or negative clipper

31 31 Clemson ECE Laboratories Clamper Circuit that shifts the DC value of an input voltage through the use of a diode and capacitor Diode conducts on negative half cycle to allow capacitor to charge Once charged, capacitor passes AC signal shifted by the charge built on C Diode polarity determines positive or negative clamping (positive pictured below) RC time constant must be much larger than input signal period

32 32 Clemson ECE Laboratories Note on circuit connection The NI-Elvis VPS is internally grounded This means no physical wire connection on your board is required to ground the voltage source For V b = 0, connect diode straight to ground For non-zero V b, connect diode to VPS supply + or supply - Connection already made within NI-Elvis board

33 33 Clemson ECE Laboratories Preparations for Next Lab Post Lab 4 – 3 questions under Lab Report Pre Lab 5 – Be familiar with BJT transistor operation and read through lab I do not require you to bring in graph paper Remember: Lab report due next week

34 34 Clemson ECE Laboratories LABORATORY 5 – BIPOLAR JUNCTION TRANSISTOR CHARACTERISTICS

35 35 Clemson ECE Laboratories Bipolar Junction Transistor Three terminal device: Collector, Emitter, Base Collect-Emitter current controlled by B-E current Four regions of operation {NPN (PNP)}: – Cutoff – Both P-N Junctions reverse biased – Saturation – Both P-N Junctions forward biased – Forward Active – B-E (B-C) forward biased, B-C (B-E) reverse biased – Inverse Active – B-E (B-C) reverse biased, B-C (B-E) forward biased N PNP NP

36 36 Clemson ECE Laboratories Output Characteristic Cutoff Forward Active Saturation

37 37 Clemson ECE Laboratories Transistor Parameters h FE = I C /I B = β – dc current gain h fe = ΔI C /ΔI B = β o – small signal (ac) current gain h ie = ΔV BE /ΔI B = r π – input resistance h oe = ΔI C /ΔV CE – output conductance h re = ΔV BE /ΔV CE – voltage feedback ratio h ie can be approximated from βV T /I CQ V A – Early Voltage

38 38 Clemson ECE Laboratories Preparations for Next Lab Post Lab 5 – 6 questions under Lab Report Pre Lab 6 – Figure 6.2 DC Sweep to find Q point – Figure 6.1 Transient analysis for various R – Use transient setup given in pre lab Remember: Electronic copy of lab report due tonight by 5 pm

39 39 Clemson ECE Laboratories LABORATORY 6 – BJT COMMON-EMITTER CIRCUIT BIAS

40 40 Clemson ECE Laboratories Common Emitter Bias Circuit Emitter is used as a reference point for both input and output R 1 and R 2 form a bias network to set a desired base current R C used to set output voltage levels R E helps reduce circuit variation with β but also reduces AC voltage gain

41 41 Clemson ECE Laboratories Q-Point Bias circuit is used to select an operating (Q) point Q point should be well into the forward active region to get a properly behaving amplifier circuit When adding a small signal AC voltage, the output voltage will shift with the AC input based on gain If the Q point is too close to saturation or cutoff, output waveform will distort and circuit will not behave as a proper amplifier

42 42 Clemson ECE Laboratories Common Emitter Amplifier AC input signal can be added to base terminal (C 1 used to filter out any DC component) V O is takes from collector terminal to ground (C 2 once again used to remove DC component) C E added to increase AC gain; Emitter is shorted to ground for AC – We will explore this more next week in Lab 7

43 43 Clemson ECE Laboratories Preparations for Next Lab Post Lab 6 – 4 questions under Lab Report Pre Lab 7 – Simulate circuit 7.1 for the 10 different configurations given in the lab manual

44 44 Clemson ECE Laboratories LABORATORY 7 – BJT COMMON-EMITTER CIRCUIT VOLTAGE GAIN

45 45 Clemson ECE Laboratories Common Emitter Amplifier Once Q point is established, small AC signal can be added to base This signal is amplified and seen at the collector terminal

46 46 Clemson ECE Laboratories Hybrid-π Equivalent Circuit Used to model BJT response to small signal AC input g m = I CQ /V T R o = V A /I CQ R π = β/g m When applied to overall circuit, can provide small signal voltage gain from input vs output transfer function

47 47 Clemson ECE Laboratories Effect of Emitter Capacitor With C E : Without C E : With C E, two sides of circuit only share a common ground; without C E, R E adds a feedback loop which produces a voltage divider, reducing V π and the gain

48 48 Clemson ECE Laboratories Frequency Response Capacitors in this circuit have been selected so they essentially provide 0 impedance at circuit operating frequency. As frequency is changed, the capacitors start to produce an appreciable impedance; thus, lowering the gain of the circuit.

49 49 Clemson ECE Laboratories Preparations for Next Lab Post Lab 7 – 4 Questions under Lab Report Pre Lab 8 – 2 Hour group design lab – Each student should read through and do design calculations individually and perform simulations Lab Report 2: Due 11/13 by 5:00 PM, electronic submission – Pick from Labs 4-7

50 50 Clemson ECE Laboratories LABORATORY 8 – BJT COMMON EMITTER DESIGN I

51 51 Clemson ECE Laboratories Equivalent Circuit R O ignored Mesh analysis provides A v Design Calculations: – h ib + R E = 235 – R ac = 2.585k – R dc = 4.935k – I CQ = 1.33 mA – V CEQ = V – V BB = V – β = 200 – I BQ = µA – h ie = 3.91k – h ib = – R E = 215 – R 2 = 4.785k – R 1 = k

52 52 Clemson ECE Laboratories Preparations for Next Lab Post Lab 8: 2 Questions under Lab Report – Do not do a full report for question 1. Simply provide me the design calculations, results, and comparison. Pre Lab 9: Individual Design Lab – Bring calculations with you to next lab – Print Lab Summary to turn in as Post Lab 9

53 53 Clemson ECE Laboratories LABORATORY 9 – BJT COMMON EMITTER DESIGN II

54 54 Clemson ECE Laboratories Equivalent Circuit R o ignored Mesh analysis V π = V s V o = -(R C //R L )g m V π A v = -(R C //R L )g m g m = I CQ /V T When R C = R L, A v = -R C I CQ /2V T

55 55 Clemson ECE Laboratories Design Calculations R ac = 2.35k I CQ = mA V CEQ = 3V V BB = V β = 200 I BQ = A h ie = 4.073k h ib = R dc = 5.797k R E = 1.097k R 2 = 28.26k R 1 = 97.92k

56 56 Clemson ECE Laboratories Preparations for Next Lab Post Lab 9 is to be turned in before you leave today Pre Lab 10 – Read through the lab and be familiar with FET operation

57 57 Clemson ECE Laboratories LABORATORY 10 – FIELD EFFECT TRANSISTORS

58 58 Clemson ECE Laboratories JFET Operation N-Channel JFET – P-type gates – N-type channel with ohmic contacts at both ends – P-Channel switches doping type positions Current flow is controlled by gate bias – VGS = 0 – Depletion regions exist between reverse biased p-n junctions, but a channel of n- type material allows current flow from drain to source – VGS << 0 – Depletion region extends completely across n-type region cutting off current flow gate

59 59 Clemson ECE Laboratories JFET Equations Linear Region – I DS = K n [2(V GS – V P ) V DS – V DS 2 ] – Where K n = I DSS /V P 2 – I DSS – 0 Voltage current V P – pinchoff voltage Saturation Region – I DS = K n (V GS(Sat) ) 2

60 60 Clemson ECE Laboratories Preparations for Next Lab Post Lab 10 – 3 questions under Lab Report Pre Lab 11 – Simulate Figure 11.6

61 61 Clemson ECE Laboratories LABORATORY 11 – FET BIAS AND AMPLIFICATION

62 62 Clemson ECE Laboratories JFET Amplifier Similar circuit layout to BJT amplifier circuits – Common-drain analogous to Common-emitter – Common-source analogous to Common-collector Voltage controlled device with negligible current draw into gate – Only reverse saturation current of p-n junctions will flow Common-drain Common-source

63 63 Clemson ECE Laboratories JFET Small Signal AC Model g m = ΔI D /ΔV GS r d = dV DS /dI D Amplification – μ = g m r d When applied to common-drain circuit: If R S = 0 or bypassed – A v = g m (r d ||R D )

64 64 Clemson ECE Laboratories Preparations for Next Lab Post Lab 11 – 3 questions under Lab Report Pre Lab 12 – Be familiar with logic gate operation – Simulate both CMOS inverter and NAND gate

65 65 Clemson ECE Laboratories LABORATORY 12 – BASIC LOGIC CIRCUITS

66 66 Clemson ECE Laboratories CMOS Logic Complementary Metal Oxide Semiconductor (CMOS) – Utilizes both pMOS and nMOS transistors Currently the most widely used technology for logic gates CMOS has helped push speeds faster and sizes smaller due to the ever improving transistor technology that allows lower voltage operation and smaller gate sizes

67 67 Clemson ECE Laboratories CMOS Inverter pMOS transistor source tied to VCC nMOS transistor source tied to GND Both gates tied together and used as input Both drains tied together and used as output When In = 5 V: pMOS off, nMOS on, Out grounded When In = 0 V: pMOS on, nMOS off, Out tied to +5

68 68 Clemson ECE Laboratories Slew Rate Slew rate refers to the rate at which signals rise and fall Rise and fall times determine how fast a circuit can operate (maximum operating frequency) Real signals do not instantaneously switch from high to low Transition times can lead to circuit glitches or missed data

69 69 Clemson ECE Laboratories The End! Enjoy the rest of your semester


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