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Company Confidential FL7733 EVT1 System Verification Report Oct.29.2013 Power Conversion Korea Inki-Park.

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Presentation on theme: "Company Confidential FL7733 EVT1 System Verification Report Oct.29.2013 Power Conversion Korea Inki-Park."— Presentation transcript:

1 Company Confidential FL7733 EVT1 System Verification Report Oct Power Conversion Korea Inki-Park

2 2 Company Confidential Schematics[8.4W]

3 3 Company Confidential Transformer Core : RM6 Inductance of Primary side : 1mH NoWindingPin(S F)WireTurnsWinding Method 1N P φ54TsSolenoid winding 2Insulation : Polyester Tape t = 0.025mm, 2Layers 3NSNS NS + NS- 0.25φ (TIW)30TsSolenoid winding 4Insulation : Polyester Tape t = 0.025mm, 2Layers 5NANA φ20TsSolenoid winding 6Insulation : Polyester Tape t = 0.025mm, 2Layers 7N P φ27TsSolenoid winding 8Insulation : Polyester Tape t = 0.025mm, 6Layers Transformer[8.4W]

4 4 Company Confidential 1. Protection 1) SCP 2) SRSP 3) SROP 4) ODSP 5) VS OVP

5 5 Company Confidential SCP Concept VS voltage at gate-off is close to zero when LED load is shorted. SCP is disabled for the initial 14 ms once V DD is higher than UVLO. 200ms JFET regulation enlarges AR time during SCP.

6 6 Company Confidential SCP Test Results SCP de-bounce cycle is 4 and operated well. Test condition: C COMI [2.2uF], C VDD [10uF]. Vin[90Vac] Ch1[V GATE ],,Ch2[V IN ], Ch3[V VS ], Ch4[I OUT ] Vin[265Vac]

7 7 Company Confidential SCP Test Results T SCP.bnk of EVT1 was larger than EVT0. JFET regulation is operated well. Test condition:, Rstr[30k], C COMI [1.0uF], C VDD [10uF]. T SCP.bnk :14ms -->OK Ch1[V DD ],,Ch2[V IN ], Ch3[V GATE ], Ch4[I OUT ] EVT0 Ch1[V GATE ],,Ch2[V IN ], Ch3[V DD ], Ch4[I OUT ] EVT1 T SCP.bnk :16ms V JFET.HL : 19V V JFET.LL : 13V

8 8 Company Confidential Current-mode SRSP Current-mode SRSP protects the condition that sensing resistor is short before VDD-ON. Vin level is be detected by Ivs and T VCS-BNK is inversely proportional to Vin level. Once V CS is maintained under 0.1V for T VCS-BNK, SRSP is triggered. Current-mode SRSP is monitored only for first switching cycle. Concept

9 9 Company Confidential Test Results SRSP is operated well. JFET regulation is operated well. Test condition: C COMI [2.2uF], C VDD [10uF]. Ton SRSP : 4.2us V JFET.HL : 19V Current-mode SRSP Vin[90Vac] Vin[265Vac] Ch1[V DD ],,Ch2[V IN ], Ch3[V CS ], Ch4[I OUT ] Ton SRSP : 1.9us V JFET.LL : 13V

10 10 Company Confidential Voltage-mode SRSP Voltage-mode SRSP protects the condition that sensing resistor is short after VDD-ON. SRSP monitoring is enabled when Vin is higher than 60% of peak Vin. Once V CS is maintained under 0.1V for SRSP monitoring time, SRSP is triggered. Concept

11 11 Company Confidential Test Results Voltage mode SRSP is operated well Test condition: C COMI [2.2uF], C VDD [10uF]. Vcs < 0.1V Rcs Short Ch1[V DD ],,Ch2[V GATE ], Ch3[V CS ], Ch4[I OUT ] ab a b Rcs Short SRSP Trigger Vin: ab A B A B Vin: ab Vin: 83V[130V *0.6]Vin: 248V[368V *0.6] Vcs < 0.1V SRSP Trigger Vin[265Vac] Vin[90Vac] Voltage-mode SRSP

12 12 Company Confidential Test Results SROP is operated well. JFET regulation is operated well. Test condition: C COMI [2.2uF], C VDD [10uF]. Ch1[V GATE ],,Ch2[V DD ], Ch3[V CS ], Ch4[I OUT ] SROP 1.0us/div100ms/div

13 13 Company Confidential Test Results OCP is triggered with just one pulse. JFET regulation is operated well. OCP[ODSP] Ch1[V GATE ],,Ch2[V CS ], Ch3[V IN ], Ch4[I OUT ] Test condition: Vin[265Vac], C COMI [2.2uF], C VDD [10uF]. Csn[20nF], Rsn[100k] 1.0us/div100ms/div V JFET.HL : 19V V JFET.LL : 13V

14 14 Company Confidential Test Results After LED opened, VDD OVP is triggered at 24.8V. VS OVP is also triggered at 3.1V after LED opened. Test condition: C COMI [2.2uF], C VDD [10uF]. OVP – VDD and VS VDD OVPVS OVP V DD : 24.8V LED Open Ch1[V GATE ],,Ch2[V DD ], Ch3[V VS ], Ch4[I OUT ] V VS : 1.56V V DD : 17.3V LED Open V VS : 3.1V

15 15 Company Confidential Test Results JFET regulation is operated well. Test condition: C COMI [2.2uF], C VDD [10uF]. OVP – VDD and VS Ch1[V GATE ],,Ch2[V DD ], Ch3[V VS ], Ch4[I OUT ] V JFET.HL : 19V V JFET.LL : 13V

16 16 Company Confidential 2. System 1) CC 2) THD/PF 3) Overshoot 4) Startup

17 17 Company Confidential ±1.05% CC 1.Test results Test condition: R VS1 [200k], R VS2 [30k], C OUT [470uF], C COMI [2.2uF] 265Vac[50Hz]230Vac[50Hz]180Vac[50Hz]140Vac[60Hz]120Vac[60Hz]90Vac[60Hz] Rcomp[200]±1.02%±0.88%±1.18%±1.19%±1.04%±1.19% Rcomp[220]±1.78%±1.48%±1.33%±1.34%±1.19%±1.49% ±0.59% Rcomp[200]Rcomp[220]

18 18 Company Confidential CC 1.Test results Test condition: R VS1 [200k], R VS2 [30k], C OUT [470uF], C COMI [2.2uF] ±0.59% EVT0EVT1 Load regulation of EVT1 is having different pattern a little from EVT0. ±0.6%

19 19 Company Confidential THD and PF Samples Io [mA]PFTHD[%] 90Vac265Vac90Vac265Vac90Vac265Vac # # Test results Test condition: C COMI [2.2uF] Vin[90Vac]Vin[265Vac] Ch3[V IN ], Ch4[I IN ]

20 20 Company Confidential Overshoot Vin level is detected by Ivs and V COMI is charged by V COMI modulator output. V COMI modulator output is inversely proportional to Vin level. Therefore, V COMI is adjusted close to steady state level during softstart time. Concept

21 21 Company Confidential Test Results VCOMI clamped at startup is inverse proportional to Vin level and operated well. There are no overshoot even fast On & OFF of AC power. Vin[90Vac] Vin[265Vac] Vin[277Vac] Overshoot – 8.4W V COMI_INT.CLP : 2.1V V COMI_INT.CLP : 1.1V Test condition: C COMI [2.2uF], C VDD [10uF], C VDD [470uF], Lm[1mH]. Ch1[V DD ],, Ch2[V IN ], Ch3[V COMI ], Ch4[I OUT ] V COMI_INT.CLP : 1.5V

22 22 Company Confidential Test Results Startup time Startup time can meet 0.2s. Test condition: Vin[90Vac], C OUT [470uF], C COMI [2.2uF], Lm[1mH] Rstr: 30k 178ms Ch1[V DD ],, Ch2[V IN ], Ch3[V OUT ], Ch4[I OUT ]

23 23 Follow us on twitter.com/fairchildSemitwitter.com/fairchildSemi View product and company videos, listen to podcasts and comment on our Visit us on


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