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Module 3 Combinational and Sequential Logic Circuit By: Cesar Mendoza

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Combinational logic: Combinational logic: When logic gates (such as AND, OR and NOT) are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved is that logic in which all outputs are directly related to the current combination of values on its inputs.

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The Exclusive-OR and Exclusive-NOR gates Exclusive-OR (XOR)

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XOR Logical Operation and Truth Table The logical operation of XOR is such that the output is high only when the two inputs are at opposite levels INPUTSOUTPUT ABX 000 011 101 110

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XOR Logical Function The two variables expression X = A B is called the Logical XOR Function

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The Exclusive-NOR (XNOR)

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XNOR Logical Operation and Truth Table The logical operation of XNOR is such that when the two inputs are opposite the output is LOW. INPUTSOUTPUT ABX 001 010 100 111

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XNOR Logical Function The expression is called the Logical XNOR Function Then the output of XNOR can be written as and it means: If A and B both are High or both Low, then X is High. Otherwise X is Low

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XNOR Logical Function Then the output of XNOR can be written as and it means: If A and B both are High or both Low, then X is High. Otherwise X is Low

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QUESTION #1 1.What is combinational logic Circuit? 2.Draw the combinational circuit for XOR gate. 3.What is the logical operation of XOR gate 4.Construct and complete 2 input Truth Table for XOR gate.

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QUESTION #2 1.What is combinational logic Circuit? 2.Draw the combinational circuit for XNOR gate. 3.What is the logical operation of XNOR gate 4.Construct and complete 2 input Truth Table for XNOR gate.

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Example of Combinational Logic Central Heating Pump

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Truth Table for Central Heating Pump SwitchesOutput Heating Switch Temp Sensor Pump offoff (Hot)off on (Cold)off onoff (hot)on on (cold)off

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Example of Combinational Logic Multiplexer

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Truth Table for Multiplexer Inputs SwitchesOutput SABQ (LED) OFF off OFF ONon OFFONOFFoff OFFON on ONOFF off ONOFFONoff ON OFFon ON on

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Sequential Logic A digital logic function made of basic logic gates (AND, OR, NOT, etc.) in which the output values depend not only on the values currently being presented to its inputs, but also on previous input values. is that logic in which the output depends on a sequence of its input values.

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Latches and Flip-Flops 1)Latches It is a bistable element that can have its output latched HIGH (Set) or LOW (Reset), hence the name S-R Latch. 1)Flip-Flops It is a synchronous bistable device that can have its output changes state only on the clock edge.

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Main difference between Latches and Flip-Flops Latch: It is active when clock either at logic high level or at low level. Flip-Flop: It is active only on the clock edges. Example of LatchesExample of Flip-Flops 1)SR Latch 2)Clocked SR Latch 3)D Latch 1)JK flip-flops 2)T-type flip-flops 3)Edge triggered D-FF

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The NOR Gate S-R Latch Cross coupled NOR Gate S-R Latch logic Circuit Latch logic symbol

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initially assume that both inputs R and S and output Q are LOW [i.e. R = S = 0 and Q = 0] 0 0 0 1 0 1 RSQ/Q 0001

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Now G2 inputs are G = 0 and S = 0, therefore G2 output is = 1. G1 inputs are Q = 1 and R = 0, therefore G1 output is Q = 0. 0 0 0 1 0 1 RSQ/Q 0001

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0 0->1 1-> 0 0 Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state. 1 0 1 1 0 1 RSQ/Q 0110

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0 1->0 0->1 1-> 0 0 Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state. 1 0 1 1 RSQ/Q 0110 0010 NC 0

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0->1 0 1->0 0->1 0101 Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state. 0101 1010 1010 RSQ/Q 0110 0010 1001 0 1

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InputsOutputsOperation RSQ 00Q No Change (same as previous) 0110The output Set to ON 1001The output Reset to OFF 11 Invalid condition unpredictable output state Table 6 Truth table for S-R Latch

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Terminology used TermsMeanings No change Latch remains in previous state (store the previous output. Latch SetThe output (Q) Set to ON (i.e. Q = 1). Latch Reset The output (Q) Reset to OFF (i.e. Q = 0). Invalid Condition Simultaneous Highs on both inputs (i.e. R = S =1) not allowed. It generates unpredictable output state.

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QUESTION #3 1.What is sequential logic circuit? 2.What is the difference between latch and flip flop? 3.Complete the Truth Table for RS Latch 4.What does No Change Means? 5.What is invalid Condition Means?

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Flashback Lesson Distinctive Shape – Rectangular Shape Symbol

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Level Triggered Latches To have control over the Latchs operation, a clock signal is applied to decide when a latch is enabled or disabled and when the output changes its state. The clock signal ensures that the device is triggered into operation at the right time and is denoted with C Clock Signal or EN Enable Signal Level Triggered latch can be defined as a logic device that changes its output state in response to a HIGH or LOW level of the clock;

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Level triggered SR Latch

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AND InputsLatchOutputsComments CKRSInputsQ 00000 NO Change As long as the clock level CK is LOW the output remain same as previous (No Change will occur). 00100 01000 01100 10000QNo Change (same as previous) 101011The output Set to ON 110100The output Reset to OFF 11111Invalidunpredictable output state Table 7 Truth table for Level Triggered SR Latch

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Level Triggered D-type Latch The D-type latch is basically a S-R latch with small circuit modification. This modification was introduced to ensure that the S and R inputs are never HIGH or LOW at the same time. So D-latch is used to eliminate the undesirable invalid state occurs in the S-R latch. The D-type latch is a Data-type circuit that can latch (store) a binary 1 or 0.

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Level Triggered D-type Latch AND Inputs Latch Inputs OutputsComments CKDRSQ 0000 NO Change As long as the CK is LOW, the output remains same as previous. 0100 10100The output Reset to OFF 11011The output Set to ON Table 8 Truth table for Level Triggered D Latch

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Question #4 What is level triggered latch means? Draw the symbol of level triggered SR latch. Draw the level triggered SR latch circuit. Complete the truth table for level triggered SR latch.

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Flashback--- Question #1: Draw the distinctive symbol and the equivalent rectangular symbol of the following basic gates: 1.AND 2.OR 3.NOT 4.NAND 5.NOR

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Review Exercise: 1.is that logic in which all outputs are directly related to the current combination of values on its inputs. a)Combinational Logic b)Sequential Logic c)Common Logic 2.The logical operation of XOR is such that the output is high only when the two inputs are at opposite levels a)OR Gate b)XNOR Gate c)XOR Gate 3.is that logic in which the output depends on a sequence of its input values. a)Combinational Logic b)Sequential Logic c)Common Logic

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Review Exercise: 4.It is a synchronous bistable device that can have its output changes state only on the clock edge. a)Flip Flop b)Latch c)Level Trigger 5.Latch remains in previous state (store the previous output. a)Latch b)No Change c)Reset 6.It is a bistable element that can have its output latched HIGH (Set) or LOW (Reset), hence the name S-R Latch. a)Flip Flop b)Latch c)Level Trigger

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