4 INTRODUCTION In this project we would implement a synchronous processor, which is latency insensitive by design. Many research is happening in the industry on this topic, since the timing issues get more harder to solve with wire delays becoming an significant factor. In current method wire delays cannot be determined until final layout, which is a significant draw back in the synchronous design phase.
6 As the size of the transistor gets smaller… -Gate delay improves -Wire delay becomes too large to ignoreLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic GateLogic Gate
7 WIRE DELAY CANNOT BE DETERMINED UNTIL THE FINAL LAYOUT
8 REQUIREMENTSStudy the MIPS (Microprocessor without Interlocked Pipeline Stages) architectureTest with two benchmarks to verify the functionality of the processorStudy Synthesis of Synchronous Elastic Architectures and implement on a MIPS processor.Compile, simulate, test, and verify each component on the DE2 development board with the Altera Cyclone II FPGA.Design controllers for Latency Insensitive Design.
9 TECHNICAL CONTENT DESIGN APPROACH CURRENT DESIGN COMPONENTS PIPELINING ELASTIC CONTROLLERSTESTING, EVALUATION, AND VERIFICATIONSOFTWARE IMPLEMENTATION
10 DESIGN APPROACH The logic design is described using VHDL Will be tested on Altera Cyclone II FPGAThe project is in two phases:Phase 1: a synchronous microprocessor will be designed and implemented.Phase2: the design will be modified to a latency insensitive microprocessor and implemented
11 COMPONENTS ALU Program Counter Instruction Memory Data Memory Registers & Register FileDecoderForwarding UnitHazard Detection UnitElastic Controllers
12 ALU (Arithmetic Logic Unit) Does the major calculations including add, AND, OR subIn MIPS, the ALU takes two 32-bit inputs and produces one 32-bit output, plus some additional signals.
14 Program Counter (PC)The register containing the address of the instruction in the program being executed.MIPS instructions are each four bytes long, so the PC should be incremented by four to read the next instruction in sequence.
15 Instruction Memory (IM) Holds the instructions of a program.This design is capable of four basic instructions:R type Instructions(includes all the ALU operations)Load/Store InstructionsLoad: read a value from a memory locationStore: write a value to a memory locationBranch if equal InstructionBranch to a given offset if two registervalues are equal.
17 Data MemoryA 32-bit register file being used for the data memory for simplicity.This model contains only 128 bytes of memory.
18 Registers AND Register File Register File: A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.Registers: Small, fast, storage units that are a part of the data path of the computer.Size: from a few bits to a few hundred bits. MIPS registers hold 32 bits.Number: from one to a few hundred. MIPS has 32 registers.
19 DecoderA logic block that has an n-bit input and 2n outputs where only one output is asserted for each input combinationBlock diagram of MIPS decode unit
20 Forwarding UnitA method of resolving the data hazard by retrieving from internal buffers rather than waiting for it to arrive from programmer-visible registers or memoHazard Detection UnitThis operates in the ID stage.Handles the data and control hazards created by the Forwarding unit.It stalls or flushes the registers to prevent unpredictable operations.
22 Pipelining Buffered, Synchronous pipelines Conventional microprocessors are synchronous circuits that use buffered, synchronous pipelines. In these pipelines, "pipeline registers" are inserted in-between pipeline stages, and are clocked synchronously. The time between each clock signal is set to be greater than the longest delay between pipeline stages, so that when the registers are clocked, the data that is written to them is the final result of the previous stage.
24 Elastic ControllersFor Latency Insensitivity, the latches in the pipeline will be replaced with Elastic Controllers.This will be done in the next semester.
25 TESTING, EVALUATION AND VERIFICATION Each component has been separately tested on Altera (FPGA).The functionality of each component is further evaluated on the FPGA and the data or the output after performing the test have been collected.The verification of the data/output has been done.
27 Software Implementation Why Software is needed: Hardware doesn’t execute MIPS assembly language code. It only stores and executes those instructions that are written in a suitable format. This binary format is called the Machine Language.Software chosen:Machine Language: As it can be used directly by the hardware for execution.Assembly Language: Since machine code is very hard to understand that is why it is needed to make it understandable and human-centric. For this, Assembly Language is selected as it is very close to Machine code.
28 Instructions Performed ALU Instructions: ADD , AND , OR , SUB , SLT , J OP Code( it is of 6 bits of length) 1St Register( 5 bits of address length)2ND Register( 5 bits of address length)16 bits of number to be performed with 2ND register.ALU InstructionOp CodeADD001000AND100100OR100101SUB100010SLT101010J000010
31 PROJECT STATUSThe first phase of the project has been achieved successfully.This second phase will be resumed starting from Spring 2011.Some work is already being done for the second phase.(Elastic Controllers)
32 UPDATED TIMELINE First Group Meeting 2 All Requirements Capture 3 SL.NOTASKSDURATION ( weeks)Person Responsible1First Group Meeting2AllRequirements Capture3Adder & Subs tractorALU instruction program for MIPS in Asm4Rid-Vid, BhaskarALU (Operations+ Unit)Encode programs in machine code4,55Implement PipelineAlgorithm for Linear Search5,66Decoding LogicAlgorithm for Sorting6,77Program Counter LogicAsm for Linear search6,88ALU InstructionsAsm for linear sorting7-9,99Load InstructionsEncoding Linear Search9-11,1010Store InstructionsEncode Sorting11Branch Instructions, ECTest Sorting12-14,1212FPGA testTest Binary search Program15,13-1513Presentation + Demo16
33 “COMPUTER ORGNIZATION AND DESIGN” BUDGETITEMDISCRIPTIONAMOUNT($)BOOK“COMPUTER ORGNIZATION AND DESIGN”50.00TOTALAPPROVED BUDGET
34 SUMMARYThe Synchronous Latency Insensitive is an effective design which can resolve the timing issues.The software segment holds a vital importance in the verification of the final design.So far we were able to accomplish our target and look towards the upcoming semester.