Presentation on theme: "THE FIVE CLASSIC COMPONENTS OF A COMPUTER."— Presentation transcript:
THE FIVE CLASSIC COMPONENTS OF A COMPUTER
Study the MIPS (Microprocessor without Interlocked Pipeline Stages) architecture Test with two benchmarks to verify the functionality of the processor Study Synthesis of Synchronous Elastic Architectures and implement on a MIPS processor. Compile, simulate, test, and verify each component on the DE2 development board with the Altera Cyclone II FPGA. Design controllers for Latency Insensitive Design.
DESIGN APPROACH CURRENT DESIGN COMPONENTS PIPELINING ELASTIC CONTROLLERS TESTING, EVALUATION, AND VERIFICATION SOFTWARE IMPLEMENTATION
The logic design is described using VHDL Will be tested on Altera Cyclone II FPGA The project is in two phases: Phase 1: a synchronous microprocessor will be designed and implemented. Phase2: the design will be modified to a latency insensitive microprocessor and implemented
ALU Program Counter Instruction Memory Data Memory Registers & Register File Decoder Forwarding Unit Hazard Detection Unit Elastic Controllers
Does the major calculations including add, AND, OR sub In MIPS, the ALU takes two 32-bit inputs and produces one 32-bit output, plus some additional signals.
The register containing the address of the instruction in the program being executed. MIPS instructions are each four bytes long, so the PC should be incremented by four to read the next instruction in sequence.
Holds the instructions of a program. This design is capable of four basic instructions : R type Instructions (includes all the ALU operations) Load/Store Instructions Load: read a value from a memory location Store: write a value to a memory location Branch if equal Instruction Branch to a given offset if two register values are equal.
Register File: A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed. Registers: Small, fast, storage units that are a part of the data path of the computer. Size: from a few bits to a few hundred bits. MIPS registers hold 32 bits. Number: from one to a few hundred. MIPS has 32 registers.
A logic block that has an n-bit input and 2n outputs where only one output is asserted for each input combination Block diagram of MIPS decode unit
A method of resolving the data hazard by retrieving from internal buffers rather than waiting for it to arrive from programmer-visible registers or memo Hazard Detection Unit This operates in the ID stage. Handles the data and control hazards created by the Forwarding unit. It stalls or flushes the registers to prevent unpredictable operations.
Buffered, Synchronous pipelines Conventional microprocessors are synchronous circuits that use buffered, synchronous pipelines. In these pipelines, "pipeline registers" are inserted in-between pipeline stages, and are clocked synchronously. The time between each clock signal is set to be greater than the longest delay between pipeline stages, so that when the registers are clocked, the data that is written to them is the final result of the previous stage.
For Latency Insensitivity, the latches in the pipeline will be replaced with Elastic Controllers. This will be done in the next semester.
Each component has been separately tested on Altera (FPGA). The functionality of each component is further evaluated on the FPGA and the data or the output after performing the test have been collected. The verification of the data/output has been done.
Why Software is needed: Hardware doesnt execute MIPS assembly language code. It only stores and executes those instructions that are written in a suitable format. This binary format is called the Machine Language. Software chosen: Machine Language: As it can be used directly by the hardware for execution. Assembly Language: Since machine code is very hard to understand that is why it is needed to make it understandable and human-centric. For this, Assembly Language is selected as it is very close to Machine code.
ALU Instructions: ADD, AND, OR, SUB, SLT, J OP Code( it is of 6 bits of length) 1 St Register( 5 bits of address length) 2 ND Register( 5 bits of address length) 16 bits of number to be performed with 2 ND register. ALU Instruction Op Code ADD AND OR SUB SLT J000010
The first phase of the project has been achieved successfully. This second phase will be resumed starting from Spring Some work is already being done for the second phase.(Elastic Controllers)
SL.NO TASKSDURATION ( weeks)Person Responsible 1 First Group Meeting2 All 2 Requirements Capture3All 3 Adder & Subs tractor ALU instruction program for MIPS in Asm4Rid-Vid, Bhaskar 4 ALU (Operations+ Unit) Encode programs in machine code 4,5Rid-Vid, Bhaskar 5 Implement Pipeline Algorithm for Linear Search5,6Rid-Vid, Bhaskar 6 Decoding LogicAlgorithm for Sorting6,7Rid-Vid, Bhaskar 7 Program Counter LogicAsm for Linear search6,8Rid-Vid, Bhaskar 8 ALU InstructionsAsm for linear sorting7-9,9Rid-Vid, Bhaskar 9 Load InstructionsEncoding Linear Search9-11,10Rid-Vid, Bhaskar 10 Store InstructionsEncode Sorting11Rid-Vid, Bhaskar 11 Branch Instructions, ECTest Sorting12-14,12Rid-Vid, Bhaskar 12 FPGA testTest Binary search Program15,13-15Rid-Vid, Bhaskar 13 Presentation + Demo16All UPDATED TIMELINE
ITEMDISCRIPTIONAMOUNT($) BOOKCOMPUTER ORGNIZATION AND DESIGN TOTAL50.00 APPROVED BUDGET50.00
The Synchronous Latency Insensitive is an effective design which can resolve the timing issues. The software segment holds a vital importance in the verification of the final design. So far we were able to accomplish our target and look towards the upcoming semester.