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A NEW 5-TRANSISTOR XOR-XNOR CIRCUIT BASED ON THE PASS TRANSISTOR LOGIC Vimal Kant Pandey.

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Presentation on theme: "A NEW 5-TRANSISTOR XOR-XNOR CIRCUIT BASED ON THE PASS TRANSISTOR LOGIC Vimal Kant Pandey."— Presentation transcript:

1 A NEW 5-TRANSISTOR XOR-XNOR CIRCUIT BASED ON THE PASS TRANSISTOR LOGIC Vimal Kant Pandey

2 Introduction XOR-XNOR circuits are the basic building block of many arithmetic and encryption circuits e.g. adders, multipliers, Comparators, Parity Checkers etc. Careful design and analysis is required for XOR-XNOR circuits to obtained –full output voltage swing, lesser power consumption and delay in the critical path. We proposed a new XOR-XNOR circuit and compare its performance with different designs. The designs are simulated using TSPICE in the voltage range of 0.6V to 1.2V using 90nm CMOS technology.

3 Previous Work In the past two decades, a number of circuit techniques have been reported with a view to improve the circuit performance of XOR- XNOR gates [3]-[4]. Shiv et al. [5], the XOR–XNOR circuit is design based on pass- transistor logic (PTL) and CMOS inverter (Fig1 ) has – lower PDP, – less power dissipation and – faster compared to design in [6] with a low supply voltage. However both of the circuits give a poor signal output voltage in certain input combination. Figure1: XOR-XNOR gate using 8 transistors in [5]

4 D. Radhakrishnan et al. [2], the XOR and XNOR circuit based on Pass Transistor Logic (PTL) using 6 transistors is reported as shown in Figure 2. It has – a full output voltage swing – better driving capability Elgamel et al. [7], has designed improved version of [2] in Fig. 3 has – has better power-delay product and – higher noise immunity. Figure 3: XOR-XNOR gate using 8 transistors in [4] Figure 2: XOR-XNOR gate using 6 transistors in [2]

5 Proposed Design The proposed design of XOR-XNOR gate and its operation is shown below: ABM1M2M3M4M5XORXNOR 00ON OFFONOFF01 01 ONOFF ON10 10 OFFONOFFON10 11OFF ON OFF01

6 Output Waveform

7 V(v)Proposed8T[5]8T[4]6[2] (5T) Delay for XOR (ns) Delay for XNOR (ns) Average power for XOR XNOR (fw) PDP for XOR (YJ) PDP for XNOR (YJ) Comparison Table

8 References 1.N. Weste, and K. Eshranghian, Principles of CMOS VLSI Design: A System Perspective, Reading MA: Addison - Wesley, D. Radhakrishanan, Low-voltage low-power CMOS full adder, in Proc. IEE Circuits Devices Syst., vol. 148, Feb K. H. Cheng, and C. S. Huang, T he novel efficient design of XOR/XNOR function for adder applications, in Proc. IEEE Int, Conf. Elect., Circuits Syst. Vol. 1, Sept. 5-8, 1999, pp M.A. Elgamel, S. Goel, and M.A. Bayoumi, Noise tolerant low voltage XOR-XNOR for fast arithmetic, in Proc. Great Lake Symp. VLSI, Washington DC, Apr , 2003, pp S. W. Shiv Shankar Mishra, R. K. Nagaria, and S. Tiwari, "New Design Methodologies for High Speed Low Power XOR-XNOR Circuits," World Academy of Science, Engineering and Technology, 2009.

9 6.S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, " Design methodologies for high- performance noise-tolerant XOR-XNOR circuits," Circuits and Syst ems I:Regular Papers, IEE T ransactions on, vol. 53, pp , M. Elgamel, S. Goel, and M. Bayoumi, "Noise tolerant low voltage XOR-XNOR for fast arithmetic," in Proceedings of the 13th ACM Great Lakes symposium on VLSI Washington, D. C. USA: ACM, W. Jyh-Ming, F.Sung-Chuan and F. Wu-Shiung, "New efficient designs for XOR and XNOR functions on the transistor level," Solid- State Circuits, IEEE Journal of, vol. 29, pp , Sung-Chuan Fang, Jyh-Ming Wang, and Wu-Shiung Feng, A New Direct design for three-input XOR function on the Transistor level, IEEE trans. Circuits Syst. I: Fundamental theory and Applications, vol. 43, no. 4, April Nabihah Ahamd, Rezaul Hasan, A New Design of XOR–XNOR gates for low power /11/ 2011, IEEE.

10 11.H. T. Bui, et aI., "New 4-transistor XOR and XNOR designs", Proceedings of The second IEEE Asia Pacific Conference on ASICs, pp , A.P. Chandrakashan, S. Sheng, and R. Brodersen, Low state Circuits, vol. 27, No. 4, pp , S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy, Design Methodologies for high performance noise tolerant XOR-XNOR circuits, IEEE Transactions on Circuits and Systems– Regular Papers, Vol. 53, No. 4, 2006, pp Hung Tien Bui, Abdul Karim Al-Sheraidah, and Yuke Wang NEW4- TRANSISTOR XOR AND XNOR DESIGNS Dept. of Computer Science & Engineering, Florida Atlantic University 777 Glades Rd., Boca Raton, Florida, USA. 15.H. T. Bui, A. K. AI-Sheraidah and Y. Wang. Design and Analysis of IO-transistor Full Adders Using Novel XOR-XNOR Gate, Technical Report. Florida Atlantic University, October 1999.

11 16. Sreehari Veeramachaneni and Hyderabad, New improved 1-bit adder cells, ECE/CCGEI, Niagara Falls. Canada, May , pp R. Shalem, E. John, and L. K. John, A novel low power energy recovery full adder cell, in Proc. IEEE Great Lakes VLSI Symp pp , Feb 1999


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