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**LOGIC FAMILIES CHAPTER : 6**

4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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GTU Dec-2010 Questions (1) With neat circuit explain the two inputs TTL NAND gate using TOTAM POLE output also mention the advantages and disadvantages of TOTAM POLE output. (2) Define the following terms: : (1) Input bias current (2) Input offset voltage (3) PSRR (4)Noise margin (5) fan-in (6) Propagation delay (7)Figure of merit for logic families (3) Describe the comparison of IC logic families. (4) Explain with neat circuit diagram Tristate TTL devices. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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GTU June-2010 Questions 1. Give the classification of Logic families. Also list the characteristics of digital IC and explain any three of them 2. List the logic family. Give comparisons of each of them. Also give the advantages and disadvantages of each logic families. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**GTU June-2011 Questions 1. Define following parameters.**

I) Fan-out, II) Propagation delay, III) Speed power product, IV) Slew rate, V) CMRR, VI) Gain bandwidth product, VII) Power dissipation. 2. Give the comparison between various logic families. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Classification based on circuit complexity**

TOPIC 01 Classification based on circuit complexity SSI: (3 to 30 gates/chip) The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI) MSI: (30 to 300 gates/chip) improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). LSI: (300 to 3,000 gates/chip.) Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates VLSI: (more than 3,000 gates/chip) Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip ULSI: At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Classification based on circuit complexity**

TOPIC 01 Classification based on circuit complexity 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 2 Various Logic Families**

(A)Bipolar transistors : (1) Saturated : RTL,DTL,DCTL,I2L,HTL,TTL (2)Unsaturated: Schottky TTL and ECL (B) Unipolar MOSFET transistors : NMOS, PMOS, and CMOS 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

3.1 Current and Voltage Parameters : VIH (min) : high- level input voltage VIL (max) : low- level input voltage VOH (min) : high- level output voltage VOL (max) : low- level output voltage IIH : high- level input current IIL : low- level input current IOH : high- level output current IOL : low- level output current 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

3.1 Current and Voltage Parameters : 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**VCC: The voltage applied to the power pins. **

3.1 Current and Voltage Parameters : VCC: The voltage applied to the power pins. VT (Threshold Voltage): The voltage level at which input pins will transition from being in one state to another. VIH (Voltage Input HIGH): Minimum positive voltage applied to an input pin which will be considered by the device as a logic HIGH. VIL (Voltage Input LOW): Maximum positive voltage applied to an input pin which will be considered by the device as a logic LOW. VOH (Voltage Output HIGH): Minimum positive voltage from an output pin which will be considered by the device as a logic HIGH 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**3.1 Current and Voltage Parameters :**

VOL (Voltage Output LOW):Maximum positive voltage from an output pin which will be considered by the device as a logic LOW. IOH (Current Output HIGH): Current flowing into an output pin in the logical HIGH state under specified load conditions. IOL (Current Output LOW): Current flowing into an output pin in the logical LOW state under specified load conditions. IIH (Current Input HIGH): Current flowing into an input pin when HIGH is applied to that input. IIL (Current Input LOW): Current flowing into an input pin when LOW is applied to that input. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Voltage Parameters 74 74S 74LS 74AS 74ALS 74F HC HCT AHC**

VOH(min) 2.4 2.7 2.5 4.9 4.4 VOL(max) 0.4 0.5 0.1 0.44 VIH(min) 2.0 3.5 3.85 VIL(max) 0.8 1.0 1.65 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

3.3 Noise Margin: 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Sinking and Sourcing Output gates are just like any other gate, they can have current flowing in two directions: into the output node (sinking), out of the output node (sourcing). We can show the output of a gate circuit as being a double-throw switch, that can connect the output terminal to either VCC or GND, depending on the position of the switch. For a gate outputting a LOW logic level, the output is analogous to the following circuit: 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Sinking and Sourcing Output gates are just like any other gate, they can have current flowing in two directions: into the output node (sinking), out of the output node (sourcing). We can show the output of a gate circuit as being a double-throw switch, that can connect the output terminal to either VCC or GND, depending on the position of the switch. For a gate outputting a LOW logic level, the output is analogous to the following Fig 1 & gate outputting a HIGH logic level, the output is analogous to the following Fig 2 4/13/2012 Figure : 1 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar. Figure : 2

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**Sinking and Sourcing Figure : 1**

4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Sinking and Sourcing Figure : 2**

4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Sinking Sourcing Figure : 1 Figure : 2 The combination of Q3 and Q4 working as a push-pull transistor pair has the ability to either source current from VCC via the output terminal and into a load, or to sink current to GND via the output terminal from a load. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Sinking and Sourcing Summarize**

The expressions sink and source relate to currents only and they refer to which direction the current is flowing. It is important to remember that logic gates can source and sink a very limited amount of current, usually in the order of a few mA. Therefore, outputs taken directly from logic gates are not enough to operate LEDs, relays, and other devices directly. The following figure illustrates a driver NAND gate that sources current when the output is HIGH and sinks current when the output is low: 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

3.2 Fan In and Fan Out Fan In: The fan-in defined as the maximum number of inputs that a logic gate can accept. If number of input exceeds, the output will be undefined or incorrect. Fan Out: The fan-out is defined as the maximum number of inputs (load) that can be connected to the output of a gate without degrading the normal operation. Fan Out is calculated from the amount of current available in the output of a gate and the amount of current needed in each input of the connecting gate. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

Fan Out: . 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Fan Out: For example, Input and output currents for the transistor-transistor logic (TTL) family are the following. Recall that negative current values indicate current flowing out of the gate while positive current values indicate current flowing into the gate: IOH = -400 µA (i.e., output can source a maximum of 400µA) IOL = 16 µA (i.e., output can sink a maximum of 16µA) IIH = 40 µA (i.e., input can sink a maximum of 40µA) IIL = -1.6 µA (i.e., input can source a maximum of 1.6µA) Therefore the fan-out is min ( 400/40, 16/1.6) = min (10, 10) = 10. In other words, each TTL gate can drive 10 other TTL gates without getting out of its guaranteed range of operation. If more than 10 gates were connected, the output voltage levels will degrade and the gate will slow down. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Fan Out: When the NOR gate output is HIGH, the output bin behaves as a current source since IOH flows out of the driver gate and into the set of driven gates. The current IOH equals the sum of all input currents indicated by IIH, flowing into the driven gates. In other words, IOH = Sum of IIH. When the NOR gate output is LOW, the output bin behaves as a current sink since IOL flows into the gate and out of the driven gates. The current IOL equals the sum of all input currents indicated by IIL, flowing out of the driven gates. In other words, IOL = Sum of IIL. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

3.3 Noise Margin: 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

Noise: Stray electric and magnetic fields can induce voltages on the connecting wires between logic circuits,These unwanted, spurious signals are called noise Noise Immunity: Circuit’s ability to tolerate noise without causing spurious changes in the output voltage. Noise Margin: Quantitative measure of noise immunity is called Noise Margin. High-state noise margin : VNH = VOH (min) - VIH (min) Low-state noise margin : VNL = VIL (max) - VOL (max) 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Ques: 3 Important characteristics of each of IC families**

High-state noise margin : VNH = VOH (min) - VIH (min) Low-state noise margin : VNL = VIL (max) - VOL (max) Any noise voltage smaller than VOH - VIH will be tolerated and will not change the output value of the driven gate. Any noise voltage smaller than VIL - VOL will be tolerated and will not change the output value of the driven gate. For TTL: VNH = 2.7V - 2.0V = 0.7V. VNL = 0.8V - 0.5V = 0.3V. For CMOS: VNH = 4.95V - 3.5V = 1.45V. VNL = 1.5V V = 1.45V. CMOS can tolerate much more noise than TTL. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**AVC: Advanced Very Low Voltage CMOS CBT: Cross Bar Technology **

LVC: Low Voltage CMOS. LV: Low Voltage. AVC: Advanced Very Low Voltage CMOS CBT: Cross Bar Technology TVC: Translation Voltage Clamp 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Propagation Delay V50% = (VOH + VOL) / 2.**

After an input to a logic gate changes, when does the output actually change? V50% = (VOH + VOL) / 2. tPHL: Difference in time between input and output signals for output to go from HIGH to V50% (see tphl in diagram above) tPLH: Difference in time between input and output signals for output to go from LOW to V50% (see tplh in diagram above) 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Figure of Merit (Speed Power Product: SPP)**

A figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (SPP) the lower, the better. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Diode-Transistor Logic**

We can also use diodes in conjunction with transistors to create Diode-Transistor Logic (or simply a DTL gate) circuits. It is better to design a DTL gate than an RTL gate because it is lot easier to create diodes than resistors on a chip. A diode on the chip may in fact be a transistor connected as a diode. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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DTL NOR Gate: We can use a diode OR circuit and couple its output to a transistor inverter (NOT) circuit in order to obtain a NOR gate. The resistance in the base circuit RB is selected to limit the base current. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**DTL NOR Gate: Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.**

4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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DTL NAND GATE We can use a diode AND circuit followed by a transistor inverter (NOT) circuit to obtain a NAND gate. The minimum voltage at C to turn on Q is 1.3 V [0.7 V for D3 and 0.6 V for Q].The maximum value of the input voltage, VIL, for the high output signal is 0.6 V [1.3 – 0.7]. Thus, the lower-noise margin is only 0.4 V. It would be better to use at least one more diode in series with D3 in order to increase the lower-noise margin. 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**DTL NAND GATE Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.**

4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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Prof.Robinson Paul , BVM Engineering College ,V.V.Nagar. Prof.Robinson Paul , BVM Engineering College , V.V.Nagar

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar.

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**Reference: http://diranieh.com/Electrenicas/DigitalAnalog.htm**

Reference: University of Connecticut 4/13/2012 Prof.Robinson Paul ,BVM Engineering College ,V.V.Nagar. Prof.Robinson Paul , BVM Engineering College , V.V.Nagar

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