Presentation on theme: "1 Improving Design Quality by Managing Process Variability ISQED 09 San Jose, CA Terry Ma."— Presentation transcript:
1 Improving Design Quality by Managing Process Variability ISQED 09 San Jose, CA Terry Ma
2 CONFIDENTIAL INFORMATION The following material is being disclosed to you pursuant to a non-disclosure agreement between you or your employer and Synopsys. Information disclosed in this presentation may be used only as permitted under such an agreement. LEGAL NOTICE Information contained in this presentation reflects Synopsys plans as of the date of this presentation. Such plans are subject to completion and are subject to change. Products may be offered and purchased only pursuant to an authorized quote and purchase order. Synopsys is not obligated to develop the software with the features and functionality discussed in the materials.
3 Introduction Sources of Process Variability Modeling Process Variability Design-Centric Process Variability Analysis Design-Centric Yield Management Summary Outline
4 Moores Scaling Source: IMEC 90nm 65nm 45nm 32nm 22nm <15nm Stress engineering implemented at 65nm enables continued scaling
5 What exactly does stress do? StressBand Structure Mobility Vt Leakage Lattice distortion Gate SiGe Si NMOS NiSi Si 3 N 4 35nm NiSi Si 3 N 4 stress cap PMOS SiGe NiSi 1.2nm Unlike humans, transistors perform better under stress!
6 If you are a designer….
7 Unfortunately, stress is everywhere… Each object (diffusion, poly, contact, well edge, …) contributes to stress!
8 If you look inside a standard cell… As much as 25% variation in current across a standard cell P N P-Channel N-Channel Transistor Position
9 Cell context can become a problem too…. Proximity EffectTypical Ambit Lithography~ 1um Mechanical Stress~ 2-3 um Well Proximity~ 1-2 um Adjacent cells Cell under analysis Ambit size 3.7x1.42.6x1.01.8x0.71.3x0.55.3x x0.35 Gate size (um 2 ) nm m m Technology Minimum gate width for 45nm node is ~0.5 um
10 DesignManufacturing Cost Slip!Slip! Time Systems Oops! The price to pay…. DesignTapeoutProduction Cost/Change 1X
11 Introduction Sources of Process Variability Modeling Process Variability Design-Centric Process Variability Analysis Design-Centric Yield Management Summary Outline
12 Sources of Layout Proximity Variation Litho ProximityMechanical Stress/StrainWell Proximity EffectPhysical VariationElectrical Variation Lithographic Proximity Shape of poly gate, diffusion region Transistor L, W Mechanical Stress Mechanical strain, defect diffusion Mobility, V th Well ProximityChannel DopingV th, Body effect Electrical VariationCircuit Variation Modeling of electrical variation (caused by physical variation) to account for proximity effects is crucial for design
13 Lithographic Proximity Variation Sub-wavelength lithography physical shape variation Physical shape variation Electrical variation CD Variation Corner Rounding Drive Current Leakage Capacitance Delay Transist or Drain Current
14 Stress-Induced I on 45nm Layout A W=100nm P2P=120nm #1 #3 #5 Layout C #1 #2 #3 #4 #5 (Transistors in Layout A are used for I on reference) Layout B #1 #2 #3 #4 #5 W=100nm
15 Implant atoms bounce off of photoresist Extra dopant in channel region changes V th, body effect Well Proximity Effect Depends strongly on well / isolation layouts
16 DL SA P2P SDP WA H SDP jogs DB DT DB Complex Layout Effects Jogs (L, H, U, Z, … shapes) SA (length of diffusion) DL (longitudinal diffusion spacing) DT (transverse diffusion spacing) SDP (active-to-dummy poly) P2P (poly space) WA (DSL and WPE) DB (distance to boundary) Poly spacing variation still exists, despite effort to follow restrictive design rules (RDR) – poly-on-grid Active diffusion jogs and corner rounding remain pervasive
24 Introduction Sources of Process Variability Modeling Process Variability Design-Centric Process Variability Analysis Design-Centric Yield Management Summary Outline
25 Litho Contour Stress xx yy zz Stress xx yy zz Seismos LX: Stress to Electrical W eq L eq Seismos CX: Contour to Electrical Layout Si Calibrated Stress Model Visualization Annotated SPICE Netlist HSPICE, HSIM, NanoSim Design-Centric Process Variability Tools
27 Model-Based Approach Accuracy Desirable 45 o target
28 Handling tricky layout… Compressive STIstress pushes Side of Diffusion edge Leads to Tensile longitudinal Stress at bottom edge In a complex layout, physics-based approach can handle very well the changes in stress behavior at diffusion corner
29 Visualizing Mobility Variation Across a Cell strong weak
31 Device and Timing Characteristics Back-annotated netlist is used for Spice simulations % Change ( dense v. sparse) ParamsNMOSPMOS Ion 6.0% 16.2% Ioff 7.0% 16.9% Delay-5.5% (fall) -13.9% (rise) SiGe + STI 3-stage ring oscillator Dense Sparse ( sparse ) ( dense )
32 Analyzing Cell Context Effects Context dependent timing variation can be evaluated to determine Sensitivity Distribution Derating factor, … Context Dependent Delay Variation BUFX4 BUF NAND2 BUF BUFX2 NAND2 Filler4 NAND2 Filler2 NAND2 (a) (b) (c) (d) (e)
33 Context analysis reveals timing variations, and best and worst case neighbors Example: 40nm 24x Inverter 100 Random Contexts – 2 Timing Arcs worst best
34 Layout Variation Typical I on variation range Typical V th variation range Length of diffusion (LOD) (SiGe or STI)~30%~50mV Spacing to adjacent diffusion~5%~15mV Active diffusion corners~5%~15mV Poly spacing~15%~30mV Poly corner rounding~5%~20mV Well boundary (WPE)/ Dual stress liner (DSL)~15%~90mV Contact to gate distance~3%~10mV Proximity Variation Summary
35 Introduction Sources of Process Variability Modeling Process Variability Design-Centric Process Variability Analysis Design-Centric Yield Exploration Summary Outline
36 Statistics and DataMining Data Visualization / Correlation Yield Management System Measurement and Inspection Wafer History Equip. History FAB ATPG Tests DFT DiagnosisFail Classification Arrays Tests Parametric Test Results Functional Test Results TEST DRC / CAA Parasitics STA LCC / CMP EDA Physical Design Data Characterization Results Test Engineer Program Fix Layout Engineer Design Fix Process Engineer Process Fix FA Engineer Faster FA New Paradigm in Yield Management Stress
37 Low Yield Lot Cell Fail By Test Failing Cell Map Spatial Trends Failing Cells and Nets Failing Nets On Layout Physical FA 50% Accurate 2-3 Days 2-3 Weeks Yield Explorer Automated Flow Multi-Tool Manual Flow Low Yield Lot Physical FA >90% Accurate Single Data Bank for yield relevant data from Design, Fab and Test An order of magnitude faster systematic failure localization Design-Centric Yield Management
38 Introduction Sources of Process Variability Modeling Process Variability Design-Centric Process Variability Analysis Design-Centric Yield Exploration Summary Outline
39 Stress engineering added to boost transistor performance at 65nm and below increases process variability Interactions between design features and physical processes result in systematic defects that can degrade design quality and yield in manufacturing Design modification made after tapeout and in manufacturing cannot fix everything and is costly For 45nm and below, design quality and yield can be improved by properly managing process variability Summary