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Outline Overview Specific Objective Design Procedures Summary of GP1 Achievements Background Theory Detailed Design Project Realization Conclusion

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Overview Recently, building low-power VLSI systems is highly in demand Most of the VLSI applications such as digital signal processing, image and video processing and microprocessors use arithmetic operations CMOS is one of the VLSI electronics that used in microprocessors, microcontrollers, and other digital logic circuits as the full adder

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Specific Objective

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Full Adder A full adder is a combinational circuit that forms the arithmetic sum of three input bits InputOutput CinABCoutSum 00000 00101 01001 01110 10001 10110 11010 11111

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Design Procedure Design Structure Level (pass Transistor, Minority Gate, TLG Gate) Sizing the transistors Width Applying Low Power Techniques Low Voltage Sub threshold

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Summary of GP1 Achievements

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Capacitive Inputs Advantages Very large fan in capability Fewer transistors and interconnections resulting in small area consumption Amount of charging and discharging currents 1.Minority FA 2.Threshold logic FA

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Minority Full Adder A minority gate has three inputs and one output and produces an output value 1 when a minority of input values adders and selection of the low power design are 1

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Minority Full Adder This design has rail to rail output signals and works properly at low voltages 0 0 1 0 01 11 0 0 1 1 0 100

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Minority Gate Implementation Using Capacitor Using Inverters

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Threshold Logic (TLG) Full Adder Advantages The total number of components are reduced such as the number of: Transistors Capacitors The output signal is regular and has a large voltage swing

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Threshold Logic (TLG) Full Adder It consists of two TLG

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(TLG) Implementation Carry StageSum Stage

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Wired Inverters Minority FA

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CMOS Inverter Voltage Transfer Characteristics The input low voltage (VIL) and the input high voltage (VIH) are identified in Figure

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Case (1): V I is more than V IH There are two cases when PMOS and NMOS operate; PMOS operating in the saturation region NMOS operating in the linear region Drain current for both transistors : CMOS Inverter Voltage Transfer Characteristics

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For NMOS transistor VGS = VI and VGS = VO; whereas for PMOS transistor, VGS = VI-VDD and VDS = VO-VDD + CMOS Inverter Voltage Transfer Characteristics

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Case (2): As VI less than VIL NMOS operating in the saturation region PMOS operating in the linear region CMOS Inverter Voltage Transfer Characteristics

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To solve for Vo, VI= VIL CMOS Inverter Voltage Transfer Characteristics

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Width Design NMOSmobility lengthVdd (V)Uo (cm2/V.)stox (cm)Cox (F)Vth (V)W (um)L (um)W/LRN (ohm) 0.18u2459.05624.08E-078.46E-070.44520.30.181.666667993.269 PMOS lengthVdd (V)Uo (cm2/V.)stox (cm)Cox (F)Vth (V)W (um)L (um)W/LRp (ohm) 0.18u2109.12314.08E-078.46E-070.437982.20.1812.22222567.3828 1:01KR=10KR=20KR=45 lengthVGB1VGB2VIHVILVIHVILVIHVIL 0.18u1.5556770.9335083281.6906881.1924931.3393270.8579181.465220.973109

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ParameterValues Voltage2V KRKR 45 Length PMOS=NMOS 0.18 µm WidthPMOS= 1 µmNMOS= 1.3µm MIN FA using wired inverters Design Results

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MIN FA Using Wired Inverters

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Average Currents & Delay Propagation Time delay: T pLH (ns)T pHL (ns)T p (ns) 1.439.220.3 Results Average Current Average Power 12849nA25698nw

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Capacitive Inputs

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Capacitive Inputs Full Adders Design

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Accept multiple inputs signals Calculates the weighted sum of all input signals Controls the ON and OFF states of the transistor The n-MOSFET switching ON or OFF depends on whether is greater than or less than the threshold voltage of the transistor

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Capacitive Inputs Full Adders Design The unique characteristic : Switching voltage can be varied according to the selected capacitor values The key factor is to start with a unit capacitance value Gate area that for 1.5mm (edge) standard CMOS process varies from 580aF/mm 2 to 620aF/mm 2 for different runs Average value has been used which is 596aF/mm 2

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Capacitors Design

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Resistors Addition and Design Most circuit simulators replace the input coupling capacitors with open circuits during DC analysis Capacitive input gate gives a degraded output level when inputs are not uniform Solution Use a very high resistor element as between the capacitive inputs gate and voltage inputs elements All Low inputs All High inputs Not Uniform inputs

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Width Design Parasitic capacitances are in the range of 100fF-400fF These capacitances cause rise and fall times of input signals to increase It is therefore necessary to resize the transistors by increasing their W/L ratios Carry StageSum Stage 9/0.18PMOS9/0.18PMOS 16/0.18NMOS25/0.18NMOS

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MIN FA Using Capacitors

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Average Currents & Delay Results Average Current Average Power 212.309nA424.618nw Propagation Time delay: T pLH (ns)T pHL (ns)T p (ns) 0.6340.3730.5

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Threshold Logic (TLG)

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Results Average Current Average Power 15837nA31674nw Propagation Time delay: T pLH (ns)T pHL (ps)T p (ns) 2.0234350.6 1.187

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Comparison Full Adder Structure 1-Bit CMOS MIN FA Using Capacitor MIN FA Using Inverters TLG FA Delay (ns)0.01650.520.3 1.187 Average Power (nW)145.1424.61825698 31674 The 1 bit CMOS full Adder Structure has a minimum power consumption

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Sub-threshold

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1-Bit Full Adder Circuit Using Pass Transistor in structure level design

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Sub-threshold

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Sub-threshold behavior of the MOS As the VTH decreases: – ID leakage – Static power – Circuit instability ID should fall to zero very quickly after VGS falls below VTH S measures by how much VGS has to be reduced for the drain current to drop by a factor of 10

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Applying Sub-Threshold Technique For 1-Bit FA Reduce the voltage of the circuit From 2 to 0.3 V Design width: By iteration

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Sub-Threshold Results Average Power P8.59pw Propagation Time delay: T pLH (ns)T pHL (ns)T p (ns) 167.75490.909192.33

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Sub-Threshold Results Full Adder1-Bit FA 1-Bit FA using sub threshold Power consumption 145nw 8.59pw Time delay 0.0165ns 192.33ns There is always a tradeoff between power consumption and the time delay for the full adder.

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Project Realization & Performance Optimization The power in full adder structure is minimized with the passage of time Started with the standard full adder structure (mirror Full Adder) the power consumption was higher than expected This led to start concerning about the power issue by looking forward new designs of full adder structures that have low power consumption As a results of this concern, it is founded today some full adder structures that are designed to consumed low power by making them contain the elements that help to reduce the power

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Low Power Structure 1. 1 bit CMOS Full Adder is a low power structure that contains a pass transistor The pass transistor helped in reducing the power by eliminating the short circuit currents since there is no voltage source and ground in it composition 2.Minority gate Full Adder using the capacitors Using capacitors will reduce the power consumption because they replace the transistors, so the amount of the short circuit currents is reduced

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Conclusion The objective of this project was achieved The low power full adder design can be achieved by applying the low power techniques to the structure Pass transistor and capacitive inputs elements Low voltage sources Sub threshold to any full adder structure The 1 bit CMOS full Adder Structure is the one that must be used when searching for low power consumption.

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