2 1) Definition of ASIC ASIC is application-specific. (vs. General-Purpose, Commodity or Standard IC i.e., memory, microprocessor)ASIC can become ASSP(Application-Specific Standard Product) if volume becomes large.(ex:MODEM, disk controller)ASIC integrates many block in one chip.(Today’s board is tomorrow’s ASIC.)
5 4) ASIC Types PLD PAL(device name), PLA(circuit style) ; FPGA all AND-OR plane logic(two-level logic)FPGAGate Array(with or without embedded block, ex;memory)Standard Cell(w. or w/o macro)Compiled block ; datapath, RAM, ROM, multiplierFull - CustomSemi-customIC(ASIC innarrow sense)
6 Important elements in ASIC Design System specificationin-houseCAD toolsIPASICdesignlibraryCommercialCAD toolsASIC foundry
7 Programmable logic device(PLD) die. The macrocells typically consist of programmable array logic followed by a flip-flop or latch. The macrocells are connected using a large programmable interconnect block.
8 Field-programmable gate array(FPGA) die. All FPGAs contain a regular structure programmable interconnect.
10 Standard & Custom Masks Two-step manufacture :First(deep)processing stepsBase wafersStandardmasksCustommasksCustomization :contacts & metal layersASIC
11 Architecture Specifications Master array = core + I/O padsCore : - macro-architecturenumber & distribution of basic core cellsembedded(specialized) structures- micro-architectureisolation method : gate or oxide isolationpredefined channels or channelless layoutavailable devices : transistors, capacitors, resistors, …NMOS/PMOS transistor count rationumber of contacts to each transistor gate, source or drainspacing between transistors, or transistor pitchidentical or variable size transistorsrelative size of the NMOS and PMOS transistorslayout of the basic core cellI/O pads - number, functional capabilities, size, ...
12 Comparison of Various ASIC Methodologies PLDs, PALs, EPLDs :< 2K gatesfield programmable AND/OR arrays with latchesuse (E)EPROM or (anti)fuse devicesfield programmable gate arrays(FPGA) :< 5K gates(1972), £ 100K gates(1998)electrically programmable SRAM, antifuse or EPROM deviceslogic mapped into predefined blocksprogrammable interconnectionsgate arrays, sea-of-gates(SOG) :£ 200K gatespersonalized with metals & contactsstandard cellcompiled cells datapath, ROM, RAMmacro-based & full-custom :all mask layers personalizeddense & high performanceRapidly changingdesignslow volumelow complexityHigh volumecomplexstable designs
13 Field Programmable Gate Arrays KFill the gap between PALs and classical(mask programmable) gate arraysarchitecture :array of configurable logic blocks(gates, multiplexers, flip-flops)predefined routing channels filled with interconnection wireswires are programmableprogramming technology : EPROM, anti-fuse, or SRAM.SRAM : volatile but reconfigurable configuration XilinxEPROM : non-volatile and reprogrammable, Alteraanti-fuse circuits : permanent programming Actelsize : up to 10K gate, (now 200K gates)speed is comparable to PALS.
14 First Generations of Gate Arrays First gate arrays :one programmable metal layerfixed contact locationsextensive use of polysilicon for routing2- or 3- transistor cell -> 2- or 3-input NAND (NOR) gateslater improvements :use several basic cells to implement more complex macrosprogrammable contactssecond programmable metal layer + viasPNPredefinedchannelPN
15 Second Generation : Sea-of-Gates CHANNELLESS LAYOUTsuppression of predefeined channelsarray entirely filled up with transistorsconnections are routed over unused transistorsGATE ISOLATION vs. OXIDE ISOLATIONsuppression of the gaps in the diffusioncontinuous strips of diffusion with equally spaced transistorsbasic cell = 1N & 1Pelectrical isolation made by connecting a gate to VSS(NMOS) or VDD(PMOS)OTHER VARIANTS & IMPROVEMENTS :embedded arraysRAM-compatible basic celladditional metal layersVDDPNVSSGate isolationVDDPNVSSOxide isolation
16 Gate Isolation vs Oxide Isolation ADVANTAGES OF GATE ISOLATION :flexibility in macro width(one transistor increment)density : transistor gate length smaller than diffusion-diffusion distancefull merging of source & drainPROBLEMS WITH GATE ISOLATION :N-and P-gate need to be physically separatedon very large & noisy circuits, glitches on power supply lines may weaken the isolation for short times
17 Channelled versus Channelless Array Flexibility in channel definition(position & width)over-the-cell routinghigher packing densityRAM-compatiblesupports variable-height cells & macrocellsnow universally usedRouting problem is simplerOK with only one metal
18 Routing Channels Alternate channels : Covering channels : Simpler reusability of classical P&R toolstunable channel width(in fixed increments)lower density(in terms of gates)gates are smallersmaller transistor sizeCovering channels :fixed channel widthincreased master cell arealarge transistor sizeboth methods can be used togetherneeds a special macro design
19 Metal Usage Signal routing : internal macro connections : metal 1 external horizontal wires(channels) : metal 1external vertical wires : metal 2metal 3&4, if any, follow direction of metal 1&2, respectively
20 Metal Usage power distribution : primary distribution : horizontal metal 1 linessecondary distribution : vertical metal 2 lines
21 Embedded StructuresA part of the core is dedicated to a special functionmost often : static RAM but also ROM, A/D or D/A converters, PLL, …also : embedded test structuresadvantages : optimized function, performance, high densitydrawback s : less versatile array, need to maintain a larger master family(price !)Core is generic and supports various customizationsreduced master family -> lower pricehigher flexibility, e.g. RAM size and location need adapted CAD tools
22 BiCMOS Master Architecture(1) Higher gate count(CMOS is denser)TTL or ECL I/Osexamples :Hitachi 84NTT 89(reduced voltage on-chip)now abandonedBiCMOS periphery blocks used for clock buffers, level conversion, …CMOS core : 60% - 95% areaexample :LSI Direct Drive Array(88)
23 BiCMOS Master Architecture(2) Variant of the previousmixed digital/analog applicationsbipolar part can contain passive elementscan be seen as an embedded arrayexample : LSI LogicHigher flexibility in the use of both devicesfull digital or mixed applicationsthe most used architectureexamples :Motorola, AMCC, Hitachi, TI, ToshibaNEC, Fujitsu