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Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Università di Parma Performance Evaluation of Ultrathin gate oxide CMOS Circuits.

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Presentation on theme: "Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Università di Parma Performance Evaluation of Ultrathin gate oxide CMOS Circuits."— Presentation transcript:

1 Alessandro Marras, Ilaria De Munari, Davide Vescovi, Paolo Ciampolini Università di Parma Performance Evaluation of Ultrathin gate oxide CMOS Circuits

2 Outline Simulation models Designed circuit Circuit analysis Conclusions Power dissipation Logic Swing and Noise Margin Frequency

3 Technology Starting technology LETI Minimum channel length 50nm Supply voltage 1.5V Measurement performed on Lot 6564 wafer12 in Udine University Projected technologies Oxide thickness from 1.5nm down to 0.9nm Supply voltage from 1.5V down to 0.9V

4 Simulation model Physical (DESSIS) simulation Projection to different t ox comparison to ideal device Circuit model EKV non-gate- permeable core HDL correction blocks Compact circuit model Physical device model

5 Device model vs. measurements

6 Ring oscillator 101 stages Gate-current effects from reasonably-sized devices (200nm X 10 m) Gate current => CMOS architecture no longer ratioless NAND gate: both static and dinamic analysis

7 t ox (nm) P ( W) LS (V)f (MHz) Ideal circuit performance Waveforms Period shortening V OH lowering V OL rising Power dissipation increase

8 Power consumption P = - Ps = (I G,n + I G,p ) · V dd /2 Static Power consumption due to gate current VHVH

9 9 Power consumption Power consumption increase, reduced by scaling down supply voltage Solution: oxynitride / high–k dielectric

10 Logic Swing degradation Logic Swing degradation, reduced by scaling down supply voltage

11 Noise Margin Reduction Logic Swing reduction Noise Margin reduction

12 Logic Swing degradation VHVH VLVL

13 Frequency shift Frequency shift, reduced by scaling down supply voltage

14 Frequency shift Complex transient due to: Additional currents tunneling through gate oxide Reduced Logic Swing Global effect observed: Frequency increase V i-1 ViVi V i+1 I Dp I Gp I Gn I Dn C VLVL VHVH

15 Conclusions Compact circuit model developed: Based on physical model Good fitting with measurements Effects of direct-tunneling current investigated: Power consumption increase Logic swing and noise margin degradation Frequency shift Circuit maintains its functionality, but with some non- negligible performance degradations Within the investigated range, permeable-gate devices seems to be suitable for practical applications


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