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Top-Gate Transistors Using Bismuth-Selenide & Indium-Arsenide Nanowires The purpose of this project was to investigate whether the use of top-gated transistors.

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Presentation on theme: "Top-Gate Transistors Using Bismuth-Selenide & Indium-Arsenide Nanowires The purpose of this project was to investigate whether the use of top-gated transistors."— Presentation transcript:

1 Top-Gate Transistors Using Bismuth-Selenide & Indium-Arsenide Nanowires The purpose of this project was to investigate whether the use of top-gated transistors would be a useful research tool in studying the physical properties of nanowires, with a secondary goal of determining whether it was possible to observe gate effect in Bismuth-Selenide based nanowire devices. It was hoped that field- effect transistors could be constructed from Bismuth-Selenide, which should theoretically display the properties of a topological insulator. If successful top-gate devices can be created, it will allow for a finer degree of control over the behaviour of nanowire transistors, allowing for greater variety of data on their physical properties to be collected. IntroductionAbstract Bi 2 Se 3 & InAs Nanowire Devices Fabrication Process Why Is A New Transistor Technology Needed? For many years, the size of transistors in integrated circuits has been constantly shrinking, resulting in the better, faster, and smaller microprocessors that are essential for the continued revolutions in the computers and other electronic devices which are so integrated into our daily lives. Much is predicated upon the ability to build ever faster computers, which has historically been closely tied to the creation of smaller and smaller silicon transistors, which are more energy efficient and can be crammed together on a chip in greater densities. The greater the density of transistors, the more powerful the device. Yet limitations imposed by fundamental quantum laws upon the manufacturing process are quickly being reached, and an alternative manufacturing technology must be sought. What Do Nanowires Offer? Nanowires, tiny wires ranging from 20nm to 100nm in diameter, offer an alternative to traditional photolithography-based techniques for creating both transistors and the wires which connect them. Rather than creating ever more elaborate photolithography techniques using interference and diffraction to create features on a chip smaller than the wavelength of the light used, a different approach is here sought. Since it is possible to grow very fine nanowires, they could allow for the bottom-up construction of microprocessors and integrated circuits smaller then currently possible, as well as investigating the properties of one-dimensional electron gases. Alex Bunkofske Faculty Advisor: Dr. Xuan Gao, Graduate Advisor: Dong Liang Department of Physics, Case Western Reserve University Background on Transistors References & Acknowledgements: The drive to miniaturization, Paul S. Peercy, Nature 406, (31 August 2000) NSF Grant DMR for funding this research. An image of the Indium-Arsenide nanowires used in this project, taken with and SEM. Note the nanometre scale bar. Computer chips; small, but not small enough. The transistor is at heart, a very small switch. It is used in modern electronic devices to both amplify and switch electrical signals within a device. A transistor is comprised of three parts; the source, the drain, and the gate. The source and drain are simply where current goes in and out of the device; the gate determines whether or not current actually flows through them. The gate is composed of a semiconductor; in most modern electronics this is silicon, in our devices it is the nanowire. The switch operates by altering the density of charge carriers in the gate material, which is possible because semi-conductors are just that; on the boundary between acting as conductors or insulators. By applying some voltage to the gate, we are able to alter the carrier density as holes and electrons are either attracted to, or repelled by, the electric potential applied. When the carrier density is altered, the amount of current able to flow through the device is also altered porportionally. This is how a transistor is able to function simultaneously as a swtich and amplifier; a very weak signal, when applied to the gate, can produce a very large change in the current going through the source and drain, by switching the gate from conductor to insulator and the entire spectrum in between. A schematic diagram of a traditional silicon- based transistor. A microscope image of a nanowire transistor, with a very large nanowire. It is pictured below in the dark field. Why Top-Gate Transistors? A diagram of the devices constructed, with a cross-section showing the different materials making up the transistor. The diagram is not to scale, but exaggerated to show design. The thicknesses of the materials atop the wafer substrate are as follows: 300 nm Silicon Dioxide, 100 nm Nickel, 40 nm Aluminum Oxide, 5 nm Titanium, 80 nm Aluminum. The average nanowire thickness was approximately 40 nm. When we wish to alter the carrier density within the nanowire, we can apply a gate voltage to either the silicon wafer (backgate) or to the top of the nanowire (topgate). Since the silicon dioxide layer is quite thick compared to the aluminum oxide layer put down, it is possible to achieve gate effect with much smaller volatges with topgate devices than backgate. The fabrication is more difficult and time-consuming, but the ability to create top-gated transistors will allow us to collect better and more varied data. Though top-gate transistors are hardly new in general, they are new to our studies of the physical properties of nanowire devices. It was also hoped that the stronger gate effect associated with top gates would permit us to observe transistor behaviour in Bi 2 Se 3 The above graphs show the gate response, or lack thereof, found in Bi 2 Se 3 nanowires. Data were collected along a range from -10 to 10 V applied to the gate electrode above the nanowire. As can clearly be seen, the material failed to display useful responses. The indium arsenide devices, graphed to the right, display very strong gate effects, as strong or stronger than the corresponding back gate effects. The strong hysteresis is due to the interaction between the compounds and ions in air and the electrodes. Had the data been taken in vacuum, there would be no hysteresis, but the presence of strong gate effect can still be noted. The graph to the left shows I vs. V curves, demonstrating that for both top and bottom gating that we have strong ohmic behaviour, and no Schottky barriers. Analysis & Conclusions 1)Nanowire Fabrication. Nanowires are grown through a vapor deposition process. A growth substrate of silicon wafer is prepared with 10nm-100nm Au spheres, which catalyze the growth of nanowires. The substance is vaporized in a low-pressure environment, and then an inert hydrogren-argon mixture carries the vapors over the growth substrate, which is placed in a cooler zone of the furnace. The gasesous source cools and forms nanowires which are generally microns long and nm in diameter. 2)Deposition on Chip. After the nanowires are grown, an alcohol based solution is prepared by the simple expedient of putting the growth substrate in alcohol and exposing it to ultrasonic energy to shake the nanowires off the growth substrate. The solution is then dropped onto Si wafers and the alcohol evaporates, leaving nanowires behind. 3)Photolithography. Through standard photolithography techniques, we then create the pattern in which we will deposit our electrodes, hoping that a large number of nanowires will happen to lie across our electrodes and gates. This step is actually executed twice, once to create the source and drain electrodes, and the second time to create the gate contacts. It is essential that the two photolithography steps be aligned as perfectly as possible, and we use a mask alignment machine to get the mask aligned with the existing pattern to plus or minus one micron for the second UV exposure. 4)Metal Deposition. After creating the pattern, we use vacuum deposition techniques to deposit ultra-thin films of extremely pure metal onto our chips. An electron gun vaporizes the metal at pressures of 5x10 -5 torr, and the chips are then placed in a remover solution where metal that was not in firm contact with the silicon is lifted off as the photoresist chemicals are dissolved. 5)Repeat. Steps 3 & 4 are repeated to create the gate electrodes. 6)Testing. After the devices have been successfully fabricated and located using dark-field microscopy, the current and voltage characteristics of the devices are then recorded and analyzed. This is done using extremely fine wires on a micro-manipulator under a microscope. Once the components of the transistor are in contact with the probes, voltages are applied and currents analyzed using labview. 7)Alternative Testing Methods: As an alternative to the probe station, we can also test single devices in the Physical Property Measurement System, which is capable of cooling the devices down to 2 Kelvin using liquid helium and applying magnetic fields of up to 9 Tesla to observe nanowire behaviour under a variety of physical conditions which can potentially affect its electrical properties. A Bismuth-Selenide nanowire. Our growth furnace and gas flow system The mask alignment machine. A picture of a nanowire device being tested on the probe station (below). 70x magnification. In considering our results, we find that there is no evidence of top-gate effect in Bi 2 Se 3 nanowires, but based on results from InAs nanowires, we believe that top-gate devices will be a valuable tool and valid technique for future work. Even when cooled to 2K, the Bi 2 Se 3 displayed no significant gate effect. The promising results from InAs devices indicate the utility of the top-gate design however.


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