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Lecture on Flip-Flops. Level-Sensitive Flip-Flop Level-sensitive flip-flop (also called a latch) Q changes whenever clock is high CLK DQ D Q 6 Transistors.

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Presentation on theme: "Lecture on Flip-Flops. Level-Sensitive Flip-Flop Level-sensitive flip-flop (also called a latch) Q changes whenever clock is high CLK DQ D Q 6 Transistors."— Presentation transcript:

1 Lecture on Flip-Flops

2 Level-Sensitive Flip-Flop Level-sensitive flip-flop (also called a latch) Q changes whenever clock is high CLK DQ D Q 6 Transistors

3 Level-Sensitive Flip-Flop NMOS transistor often replaced with transmission gate Transmission gate includes both NMOS and PMOS transistors because NMOS good at passing 0 and PMOS good at passing 1 CLK DQ DQ Transmission Gate CLK 6 Transistors 8 Transistors

4 Master-Slave Edge-Triggered Flip-Flop Can connect two level-sensitive latches in Master-Slave configuration to form edge-triggered flip-flop Master latch catches value of D at Q M when CLK is low Slave latch causes Q to change only at rising edge of CLK CLK DQ D QMQM Master Latch Slave Latch QMQM 2 x 8 = 16 Transistors Q CLK

5 Master-Slave Edge-Triggered Flip-Flop QD CLK SLAVEMASTER CLK 2 x 8 = 16 Transistors QMQM

6 More Efficient Master-Slave Edge-Triggered Flip-Flop Called a C 2 MOS (Clocked CMOS) design 8 Transistors QD CLK V DD GND CLK V DD GND MASTERSLAVE

7 Using Logic Gates to Build Flip-Flops From previous slides, you can see that its possible to build an edge-triggered flip-flop using just 8 transistors In a conventional Digital Logic course, transistor-level flip-flop designs are not usually taught Instead, flip-flop designs using cross-coupled logic gates are usually taught

8 RS-Latch as Cross-Coupled NOR Gates If R = 1, Q resets to 0 If S = 1, Q sets to 1 If RS = 00, no change RS = 11 is not allowed because leads to oscillation R S Q Q 0 0 1 1 0 1 S R No change 0 1 Undefined Q

9 Level-Sensitive RS-Latch Q only changes when CLK is high (i.e. level-sensitive) When CLK is high, behavior same as RS latch S R Q Q CLK 1 0 0 1 0 1 1 1 0 1 1 1 CLK S R No change 0 1 Undefined Q 0 X XNo change

10 Level-Sensitive D-Latch Make level-sensitive D-latch from level-sensitive RS-latch by connecting S = D and R = not D Compared to transistor version D Q Q CLK DQ 8 Transistors 18 Transistors

11 Master-Slave configuration Compared to transistor version Master-Slave Edge-Triggered Flip-Flop 8 Transistors 36 Transistors GND QD CLK V DD CLK V DD Q D CLK MASTERSLAVE

12 Alternative Edge-Triggered Flip-Flop D Q Q CLK QD V DD GND CLK V DD GND 8 Transistors24 Transistors

13 JK Flip-Flop from D-Latch Same as RS-Latch except toggle on 11 D Latch CLK Q Q J K JK-FF CLK J K Q 1 0 0 1 0 1 1 1 0 1 1 1 CLK J K No change 0 1 Toggle Q 0 X XNo change

14 Toggle Flip-Flop from D-Latch Toggles stored value if T = 1 when CLK is high D Latch CLK Q T T-FF CLK TQ 1 0 1 CLK T No change Toggle Q 0 XNo change


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