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IBIS Open Forum Teleconference January 26 th, 2007 BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi Giacomo Bernardi Roberto Izzi STMicroelectronics Flash Memory Group R&D CAD

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 1 Agenda IBIS Gate Modulation solution: ST Proposal overview Implementation and Validation by the VHDL-AMS IBIS architecture Potential implementation of the STs proposal inside a transistor-level EDA tool BIRD98 & ST proposal convergence Conclusions

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 2 IBIS Gate Modulation Criticality Effective (SPICE) working point evolution The IBIS simulation of a simultaneous switching noise does not model correctly the MOS Vgs voltage variation because the working point can move only along the same Vgs =VDD characteristic. The higher is the bouncing noise, the higher is the mismatching between IBIS and Spice results DRIVERCONTROL LOGIC ctr Input/data VDD Vgs Vgs=VDD IBIS working point evolution

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 3 Benchmark SPICE vs IBIS Standard (IBIS-STD) SSO – Rise Transition Output Power/Ground SPICE IBIS-STD SSO – Fall Transition Output Power/Ground SPICE IBIS-STD Max Delay 22% Max overshoot/undershoot 25% Diff. Power supply 32% Relative Percentage Error Initial case of study: Simultaneous Switching Output (SSO) simulations by IBIS standard (IBIS-STD), compared with the related SPICE ones, have revealed strong discrepancies. Initially, no equivalent load/impedance has been considered on the power and ground nodes of IBIS models. Test-case: 128M Nor Flash Memory (120nm)

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 4 Gate Modulation Coefficients I_effective = Kssn(Vgs,Vds)*I_IBIS-STD I(Vgs, Vds) = Kssn(Vgs,Vds)*I(Vgs=VDD,Vds) IBIS standard current Effective SPICE current The ST Gate Modulation solution is based on the introduction of two coefficients, one for the Pullup and one for the Pulldown stage, which modulate properly the IBIS standard current (I_IBIS-STD) when a bouncing noise occurs on the power and ground nodes

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 5 Kssn(Vgs, Vds) Implementation by Table-format IBIS DEVELOPER The effort has been focused on identifying a table-format implementation of Kssn coefficients, which could also be the best trade-off between accuracy and development/simulation time How can I interpolate them? Is this approach convenient in terms of development and simulation time? Vgs=VDD Table n How many I(Vgs, Vds=K) or I(Vgs=K, Vds) tables are needed? I(Vgs, Vds =K) Tables Table 1Table n Table 1 I(Vgs=K, Vds) Tables Note: K means constant value!!!

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 6 Gate Modulation Coefficient Characteristics Vds Kssn MOS Saturation zone MOS Linear zone The Kssn coefficient is independent from the Vds voltage in the saturation zone and, approximatively, also in the linear zone, in the case of small Vgs changes. It implies that one table Kssn(Vgs, Vds=K), with K in the saturation zone, can be enough for Pullup and Pulldown, respectively. Therefore, a Two-Table approach may be a good compromise accuracy-complexity. Vds = K Vgs > VDD Kssn > 1Ieffective > I_IBIS-STD Vgs < VDD Kssn < 1Ieffective < I_IBIS-STD Vgs = VDD Kssn = 1Ieffective = I_IBIS-STD Corrective behaviour of the Kssn coefficient

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 7 Two-Tables Solution K has been chosen equal to VDD Kssn(Vgs, Vds=VDD) implies that the effective current to be drawn is I_effective_pulldown=I(Vgs, Vds=VDD) I_effective_pullup=I(Vsg, Vsd=VDD) Vds Saturation zone Linear zone Kssn Vds=VDD Vgs=VDD

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 8 Effective Currents Extraction Pulldown I(Vgs, Vds=VDD) table extraction Pullup I(Vgs, Vds=VDD) table extraction Kssn_pulldown Kssn_pullup I(Vgs, Vds=VDD) Table I(Vsg, Vsd=VDD) Table I_effective =Kssn*I_IBIS-STD Since it is not possible to change the proprietary code of EDA tools that manage the IBIS models, the unique way identified for implementing and validating the solution has been to use the VHDL-AMS IBIS architecture, adding the Gate modulation coefficients algorithm. ? Vsweep=[-VDD, VDD]; Vgate is kept stable -- the collected effective current is related to the source voltage (Vs) changes VHDL-AMS

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 9 Extension of the IBIS VHDL-AMS Implementation entity IBIS_IO is generic (C_comp : real := 4.55e-12; ………………………………………………………………………… [Pullup Reference] and [Pulldown Reference] values V_pu_ref : real := 5.0; V_pd_ref : real := 0.0; Vectors of the IV curve tables I_pc : real_vector := ( 0.08, 0.00, 0.00, 0.00); ………………………………………………………………………..… if (Extrapolation = "IV") and (X <= Xdata(0)) then m := (Ydata(1) - Ydata(0)) / (Xdata(1) - Xdata(0)); yvalue := Ydata(0) + m * (X - Xdata(0)); return yvalue; …………………………………………………………………….......... IBIS VHDL-AMS Traditional IBIS (Muranyi) I-V tables: Pullup&Power_clamp V-t tables: Rising & Falling waveform Ramp values: dV/dt_r; dV/dt_f C_comp values Kssn-pulldown & Kssn-pullup I_effective = Kssn*I_IBIS-STD + Gate Modulation Algorithm I(Vgs,Vds=VDD)Pulldown table I(Vsg,Vsd=VDD) Pullup table

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 10 Implementation and Validation Strategy NOR Flash memories test-cases SSO simulations have been carried out The IBIS VHDL-AMS implementation (IBIS- AMS) has been used The Gate modulation algorithm has been added to the IBIS VHDL-AMS initial code Equivalent impedance of power rails is also been considered VDD_IO GND_IO IN EN OUT IBIS VHDL-AMS VDD VDD_IO GND_IO GND Kssn_Pullup Kssn_Pulldown +

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 11 Benchmark SPICE vs IBIS-AMS SPICE IBIS-AMS SPICE IBIS-AMS SSO – Rise Transition Output Power/Ground Output Power/Ground SPICE IBIS-AMS SPICE SSO – Fall Transition Relative Percentage Error Max Delay 3% (22% IBIS-STD) Max overshoot/undershoot 8% (25% IBIS-STD) Diff. Power supply 1% (32% IBIS-STD) Test-case: 128M Nor Flash Memory (120nm) A remarkable improvement has been achieved by implementing the ST Gate Modulation solution in the IBIS-AMS architecture. Note: The main contribution on recovering the error on the power/ground signals is due to the equivalent impedance put on the power nodes.

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 12 IBIS-STD vs SPICE vs IBIS-AMS Comparison Additional benchmarking results, extracted recently by SSO simulations on a 512Mb NOR Flash Memory (90nm). Probing on packages ball Probing on ICs pad IBIS-AMS_ball SPICE_ball IBIS-STD_ball IBIS-AMS_pad SPICE_pad IBIS-STD_pad

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 13 Potential Implementation of the ST Proposal into a Transistor-Level EDA Tool A possible IBIS-STD statement might be: _IO_xx NN {NN} file="path…………………………….. + component=componet_name………………………. + model="model_name" pin="pin_name………….. + power=on|off………………………………………………. + VI_Corner=typ|min|max………………….…………... + ISSO_PD=typ|min|max ISSO_PU=typ|min|max ……………………………………………………………….…….. ISSO_PD and ISSO_PU might be the two additional keywords linked to the I(Vgs, Vds=VDD) tables: | |Note: VDD=1.8V | [ISSO_PD] | voltage I(typ) I(min) I(max) | -1.8000V 372.1000mA 302.8200mA 459.2100mA -1.7640V 357.0800mA 292.1800mA 440.5700mA …………………………………………………………………………………………….. 1.7280V -10.7480pA -116.7800pA 3.0124nA 1.8000V -108.0300pA -163.1300pA 85.4930pA | | [ISSO_PU] | | voltage I(typ) I(min) I(max) | 0.0000V -37.7430pA -85.2600pA -19.4290pA 36.0000mV -75.5960pA -181.7600pA -24.4690pA …………………………………………………………………………………………… …………………………………………………………………………………………... 3.5280V -16.0840mA -13.1350mA -19.8970mA 3.6000V -16.5140mA -13.3920mA -20.4060mA | Current IBIS-STD driver representation into Eldo (Mentor Graphics transistor-level tool) If the ST proposal was implemented in Eldo, the pullup and pulldown equations would become: K_ssn_pullup*Ku*Iu(V-Vpur) K_ssn_pulldown*Kd*Id(V-Vpdr)

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 14 BIRD98 & ST Proposal Convergence Today it is mandatory to provide to the IBIS community a reliable solution to the Gate Modulation problem. In fact, it is becoming a heavy bottleneck in every applications in which the SPICE simulations are not a possible alternative. Especially in the context of system-in-package design, where third parties components may only be simulated by IBIS, and the power noise is critical because the ground planes are usually missing, it is impossible to predict fails before of the prototype- phase. Moreover, it has to be considered that the SPICE simulations seem too time-expensive, as IBIS alternative, in verifying the modern- system, whose complexity is rapidly increasing. The BIRD98 proposal is already a good solution for solving the Gate Modulation Effect, but two changes are advised for making it much more accurate and general purpose. As well as for matching the ST proposal, validated by the IBIS-AMS implementation.

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 15 BIRD98 Suggested Change (1) GNDQ VDDQ VDD Output pad Final StageControl Logic To consider the instantaneous source voltage value (Vs) instead of the power supply one for the current scaling. This approach is more general purpose. In fact, it is not always true that the Vgs instantaneous value is the same of the power supply one during a bouncing noise. A typical case is when the control logic and the final stage are supplied with different supply voltages. Vgs = (Vdd – Vgndq) Vgs (Vddq – Vgndq)

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 16 BIRD98 Suggested Change (2) It is preferable to draw the effective pullup (pulldown) currents by disconnecting the pulldown (pullup) stage from the pad, instead of the short current. In fact, to short the output pad to the reference node causes a change into the correct behaviour of the control logic driving capability when the control logic and the final stage are supplied by the same supply voltage. Below are reported the two advised circuits for drawing the effective pullup and pulldown currents

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 17 ST Proposal - Lowlights The Millers capacitances (AC effects) are not included The final-stages Ron instantaneous change is still a little bit under estimated compared to spice behaviour This proposal has been developed and validated only for CMOS driver

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 18 ST Proposal - Highlights It is a table-format solution Validated by the IBIS-AMS architecture on several test-cases Good trade-off between accuracy and complexity (both development and simulation time) Does not reveal proprietary information (full compliant with IBIS philosophy) Easy implementation into transistor-level EDA tools This proposal seems a reliable way for solving rapidly the gate modulation problem, which makes IBIS unusable in every non- ideal power supply simulation.

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BIRD98 and ST Gate Modulation Solution Convergence Antonio Girardi, Giacomo Bernardi, Roberto Izzi January 26 th, 2007 19 Reference Documents BIRD98 proposal (Arpad Muranyi, Intel) http://www.vhdl.org/pub/ibis/birds/bird98.txt IBIS Simultaneous Switching Output Simulations Criticality (A. Girardi, STMicroelectronics) http://www.vhdl.org/pub/ibis/futures/ST_Vgs_Presentation.pdf IBIS Gate Modulation Effect Proposal (A. Girardi, STMicroelectronics) http://www.vhdl.org/pub/ibis/futures/ST_IBIS_Gate_Modulatio n_Effect.pdf IBIS Gate Modulation Effect (STMicroelectronics Proposal) (A. Girardi, G. Bernardi, R. Izzi, STMicroelectronics)

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