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ECE C03 Lecture 41 Lecture 4 Combinational Logic Implementation Technologies Hai Zhou ECE 303 Advanced Digital Design Spring 2002

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ECE C03 Lecture 42 Outline Review of Combinational Logic Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic Multiplexers/Decoders ROM READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

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ECE C03 Lecture 43 Programmable Arrays of Logic Gates Until now, we learned about designing Boolean functions using discrete logic gates We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure Specific functions can be programmed Can use programmable logic arrays (PLA) or programmable array logic (PAL)

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ECE C03 Lecture 44 PALs and PLAs Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

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ECE C03 Lecture 45 Why PALs/PLAs Work Example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Equations Personality Matrix Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side:

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ECE C03 Lecture 46 Example of PALs and PLAs All possible connections are available before programming

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ECE C03 Lecture 47 Example of PALs and PLAs (Contd) Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them

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ECE C03 Lecture 48 Alternative Representations Short-hand notation so we don't have to draw all the wires! Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

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ECE C03 Lecture 49 Design Example ABC A B C A B C F1F2F3F4F5F6 F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xnor B xnor C Multiple functions of A, B, C

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ECE C03 Lecture 410 Differences Between PALs and PLAs PAL concept implemented by Monolithic Memories constrained topology of the OR Array A given column of the OR array has access to only a subset of the possible product terms PLA concept generalized topologies in AND and OR planes

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ECE C03 Lecture 411 Design Example: BCD-to-Gray Code Converter Truth Table K-maps W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' Minimized Functions: AB CD 00011110 00 01 11 10 D B C A 00X1 01X1 01XX 01XX K-map forW AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 00XX 00XX K-map forX AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 11XX 11XX K-map forY AB CD 00011110 00 01 11 10 D B C A 00X1 10X0 01XX 10XX K-map forZ

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ECE C03 Lecture 412 Programmed PAL 4 product terms per each OR gate A B C D 0 0 0 0 0 0

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ECE C03 Lecture 413 Non-Gate Logic AND-OR-Invert PAL/PLA Generalized Building Blocks Beyond Simple Gates So far we have seen: Kinds of "Non-gate logic": switching circuits built from CMOS transmission gates multiplexer/selecter functions decoders tri-state and open collector gates read-only memories

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ECE C03 Lecture 414 Steering Logic: Switches Voltage Controlled Switches Metal Gate, Oxide, Silicon Sandwich Diffusion regions: negatively charged ions driven into Si surface Si Bulk: positively charged ions By "pulling" electrons to the surface, a conducting channel is formed "n-Channel MOS" n-type Si p-type Si

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ECE C03 Lecture 415 Switching or Steering Logic Voltage Controlled Switches Logic 0 on gate, Source and Drain connected Logic 1 on gate, Source and Drain connected

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ECE C03 Lecture 416 Logic Gates with Steering Logic Logic Gates from Switches +5V A A A B A B +5V A B A + B Inverter NAND Gate NOR Gate Pull-up network constructed from pMOS transistors Pull-down network constructed from nMOS transistors

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ECE C03 Lecture 417 Inverter with Steering Logic Inverter Operation +5V "1" "0" +5V "0" "1" Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND Input is 0 Pull-up conducts Pull-down does not conduct Output connected to VDD

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ECE C03 Lecture 418 NAND Gate with Steering Logic NAND Gate Operation A = 1, B = 1 Pull-up network does not conduct Pull-down network conducts Output node connected to GND A = 0, B = 1 Pull-up network has path to VDD Pull-down network path broken Output node connected to VDD +5V "1" "0" +5V "0" "1"

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ECE C03 Lecture 419 NOR Gate with Steering Logic NOR Gate Operation +5V "0" "1" +5V "1" "0" A = 0, B = 0 Pull-up network conducts Pull-down network broken Output node at VDD A = 1, B = 0 Pull-up network broken Pull-down network conducts Output node at GND

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ECE C03 Lecture 420 CMOS Transmission Gate nMOS transistors good at passing 0's but bad at passing 1's pMOS transistors good at passing 1's but bad at passing 0's perfect "transmission" gate places these in parallel: InOut Control InOut Control In Out Control Switches Transistors Transmission or "Butterfly" Gate

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ECE C03 Lecture 421 Selection/Demultiplexing S S I 0 I 1 S S Z Selector: Choose I0 if S = 0 Choose I1 if S = 1 S S 0 I 1 S S Z Z Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1

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ECE C03 Lecture 422 Use of Multiplexers or Demultiplexers So far, we've only seen point-to-point connections among gates Mux/Demux used to implement multiple source/multiple destination interconnect A B Z Y Multiplexers Demultiplexers A B Z Y MultiplexersDemultiplexers

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ECE C03 Lecture 423 Well-formed Switching Logic Problem with the Demux implementation: multiple outputs, but only one connected to the input! The fix: additional logic to drive every output to a known value Never allow outputs to "float" 0 I S S Z S 1 Z "0" S S S

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ECE C03 Lecture 424 Use of Multiplexers/Selectors Multi-point connections MUX DEMUX A B Sum A0A1B0 B1 SaSb Ss S0S1 Multiple input sources Multiple output destinations

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ECE C03 Lecture 425 I 1 0 0 0 0 1 1 1 1 I 0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 A 0 1 Z I 0 I 1 General Concept of Using Multiplexers 2 data inputs, n control inputs, 1 output used to connect 2 points to a single point control signal pattern form binary index of input connected to output n n Two alternative forms for a 2:1 Mux Truth Table Z = A' I + A I 01 Functional form Logical form

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ECE C03 Lecture 426 Use of Multiplexers/Selectors Z = A' I + A I 01 Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 In general, Z = m I 2 -1 n k=0kk in minterm shorthand form for a 2 :1 Mux n 2:1 mux I 0 I 1 A Z I 0 A I 1 I 2 I 3 B Z 4:1 mux I 0 A I 1 I 2 I 3 B Z 8:1 mux C I 4 I 5 I 6 I 7

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ECE C03 Lecture 427 Alternative Implementation Gate Level Implementation of 4:1 Mux Gate Level Implementation of 4:1 Mux Transmission Gate Implementation of 4:1 Mux Transmission Gate Implementation of 4:1 Mux thirty six transistors twenty transistors I3 I0 I2 I1 A B Z

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ECE C03 Lecture 428 Design of Large Multiplexers Large multiplexers can be implemented by cascaded smaller ones Control signals B and C simultaneously choose one of I0-I3 and I4-I7 Control signal A chooses which of the upper or lower MUX's output to gate to Z 0 1 S 0 1 S 0 1 S 0 1 S 0 1 S1 2 3 S0 C AB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 C C C Z Alternative 8:1 Mux Implementation 4:1 mux 4:1 mux 8:1 mux 2:1 mux 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 Z ACB I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 0 1

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ECE C03 Lecture 429 Multiplexers/Selectors as General Purpose Blocks 2 :1 multiplexer can implement any function of n variables n-1 control variables; remaining variable is a data input to the mux n-1 Example: F(A,B,C) = m0 + m2 + m6 + m7 = A' B' C' + A' B C' + A B C' + A B C = A' B' (C') + A' B (C') + A B' (0) + A B (1) 8:1 MUX 1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7S2 S1 S0 ABC F "Lookup Table" S1 S0 AB 4:1 MUX 0 1 2 3 C C 0 1 F A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 C C 0 1

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ECE C03 Lecture 430 I 1 1 1 1 1 0 I n 0 1 I n 0 0 0 … FI 2 I n 0 1 … Generalization of Multiplexer/Selector Logic n-1 Mux control variables single Mux data variable Four possible configurations of the truth table rows Can be expressed as a function of In, 0, 1 Example: G(A,B,C,D) can be implemented by an 8:1 MUX: K-map Choose A,B,C as control variables Multiplexer Implementation TTL package efficient May be gate inefficient TTL package efficient May be gate inefficient G 8:1 mux 0 1 2 3 4 5 6 7 ABC S 2 S 1 S 0 1 D 0 1 D D D D

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ECE C03 Lecture 431 Decoders/Demultiplexers Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of output to which the input is connected data input usually called "enable" (G) n 1:2 Decoder: O0 = G S; O1 = G S 2:4 Decoder: O0 = G S0 S1 O1 = G S0 S1 O2 = G S0 S1 O3 = G S0 S1 3:8 Decoder: O0 = G S0 S1 S2 O1 = G S0 S1 S2 O2 = G S0 S1 S2 O3 = G S0 S1 S2 O4 = G S0 S1 S2 O5 = G S0 S1 S2 O6 = G S0 S1 S2 O7 = G S0 S1 S2

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ECE C03 Lecture 432 Alternative Implementations 1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable 2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable Output0 G Select Output1 Output0 /G Select Output1 Select0Select1 Output2 Output3 Output0 G Output1 Select0Select1 Output2 Output3 Output0 /G Output1

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ECE C03 Lecture 433 Switch Level Implementations Select G Output 0 Select Output 1 Select "0" Select G Output 0 1 Naive, Incorrect Implementation All outputs not driven at all times Correct 1:2 Decoder Implementation

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ECE C03 Lecture 434 Switch Implementation of 2:4 Decoder Operation of 2:4 Decoder S0 = 0, S1 = 0 one straight thru path three diagonal paths

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ECE C03 Lecture 435 Decoder as a Logic Building Block Decoder Generates Appropriate Minterm based on Control Signals Example Function: F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D') 3:8 dec 0 1 2 3 4 5 6 7 ABC Enb ABC S 2 S 1 S 0

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ECE C03 Lecture 436 A B C D A A A A A A A A A A A A A A A F 1 F 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A S 3 S 2 S 1 S 0 4:16 dec Enb BCD F 2 Decoder as a Logic Building Block If active low enable, then use NAND gates!

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ECE C03 Lecture 437 Read-Only Memories ROM: Two dimensional array of 1's and 0's Row is called a "word"; index is called an "address" Width of row is called bit-width or wordsize Address is input, selected word is output Dec 0n-1 Address 2 -1 n 0 +5V Word Line 0011 Word Line 1010 Bit Lines j i Internal Organization

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ECE C03 Lecture 438 Implementing Logic with ROMs F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' addressoutputs ROM 8 words ¥ 4 bits ABCF 0 F 1 F 2 F 3 B 0 0 1 1 0 0 1 1 AddressWord Contents A 0 0 0 0 1 1 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 0 0 1 1 0 0 F 1 0 1 1 0 0 0 0 1 F 2 1 1 0 0 1 0 0 0 F 3 0 0 0 1 1 0 1 0 by

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ECE C03 Lecture 439 ROMs vs PLAs Not unlike a PLA structure with a fully decoded AND array! Not unlike a PLA structure with a fully decoded AND array! ROM vs. PLA: ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions ROM problem: size doubles for each additional input, can't use don't cares PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions PAL problem: constrained fan-ins on OR planes Memoryarray 2 n words by m bits m output lines n address lines Decoder 2 n word lines

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ECE C03 Lecture 440 Summary Review of Combinational Logic Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic Multiplexers/Decoders ROM READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

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