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Laboratory for Sub-100nm Design Department of Electrical and Computer Engineering Novel dual-V th independent-gate FinFET circuits Masoud Rostami and Kartik.

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Presentation on theme: "Laboratory for Sub-100nm Design Department of Electrical and Computer Engineering Novel dual-V th independent-gate FinFET circuits Masoud Rostami and Kartik."— Presentation transcript:

1 Laboratory for Sub-100nm Design Department of Electrical and Computer Engineering Novel dual-V th independent-gate FinFET circuits Masoud Rostami and Kartik Mohanram Department of Electrical and Computer Engineering Rice University, Houston, TX

2 Outline n Introduction and motivation n Background n Dual-V th independent-gate FinFETs n Logic design n Simulation results n Conclusions and future directions 2

3 Introduction n Technology scaling Process variations Leakage power Short channel effects n Planar double-gate FETs and FinFETs Compatibility with planar CMOS Scalability Suppression of short channel effects Low parametric variations High I on /I off 3

4 Motivation n Conventional FinFETs Tied-gate devices n Independent-gate FinFETs Removing top oxide Electrically isolated, electrostatically coupled gates Muttreja, Agarwal, and Jha, ICCD, 2007 Caciki and Roy, IEEE TED, 2007 Tawfik and Kursun, Microelectronics Journal, 2009

5 Motivation n Conventional FinFETs Tied-gate devices n Independent-gate FinFETs Low-power logic gates Disabled, reverse-biased back-gate Independent-gate logic gates Merge parallel transistors, compact logic

6 Motivation n Merge series transistors? n Dual-V th independent-gate FinFETs Device design considerations

7 Motivation n Merge series transistors? n Dual-V th independent-gate FinFETs Device design considerations n Independent-gate dual-V th FinFETs Logic design opportunities Compact logic gates New family of logic gates Delay+power+area evaluation

8 Background n FinFET Cross-sectional view Front Gate Back Gate Source n+ Channel (undoped) Drain n+ t ox t si L Underlap

9 Background n FinFET models University of Florida double-gate (UFDG) Physics-based, good agreement with manufactured devices Fin height, silicon thickness, S/D doping, underlap, gate electrode work-function Predictive technology model (PTM) Modeled as two parallel coupled SOI devices 9

10 Background n Finfet threshold voltage V T n Φ ms and C ox tuning n Independent-gate FinFETs Electrically isolated, electrostatically coupled V th -dependence model [Colinge 2008] V th-front = V th-front 0 – δ (V gbs – V th-back ) if V gbs < V th-back V th-front = V th-front 0 in all other cases Substrate-like effect in planar CMOS 10

11 Dual-V th FinFETs n Φ ms tuning Two additional mask steps n C ox tuning through t ox Asymmetric oxides [Masahara, IEEE EDL 2007] n Device design using UFDG model

12 V GS (V) I DS (A) V DS = 1V Dual-V th FinFETs

13 n TCAD simulations (2D Sentaurus) Same device geometry 2D SentaurusUFDG

14 Dual-V th FinFETs 2D Sentaurus UFDG

15 Dual-V th FinFETs n Good V th separation n Good noise margin (approx. 0.5V dd ) n Leakage current in high-V th device pA for low-V th devices nA for high-V th devices in disabled-gate mode Comparable to 32nm CMOS

16 Dual-V th logic gates n Rules for pull-down and pull-up network: Parallel structure series structure Weak AND-like high-V th transistor strong OR- like low-V th transistor 16

17 Dual-V th logic gates

18 Novel dual-V th logic gates n Novel logic gates Independent back-gate as independent input n-input gate with n, n+1, …, 2n inputs Example f = (a + b)(c + d) n = 2, 12 unique combinations Some competitive, some not n Exponential in n Occupancy problem Series-parallel graphs Functionally equivalent, electrically different gates

19 Results n Technology libraries for n = 3 Basic library Traditional INV, NAND, NOR, AOI, OAI Previous work library = Basic library + Compact gate with parallel transistors merged Low power gates with disabled back-gate Merged series = Previous work library + Dual-V th logic gates, with series transistors merged as appropriate Complete library = Merged series library + Novel dual-V th logic gates

20 Results n ISCAS and OpenSPARC circuits n Area (no. of fins), delay, total power Improvements: Basic, Previous work, Merged series n Area savings: 27%, 23%, 12% n Delay improvement: 7%, 7%, 1% n Total power: 24%, 21%, 15% Static power X higher, but net contribution negligible Dynamic power Dominates Improvements with proposed complete library significant

21 Conclusions n Dual-V th FinFET design Gate work-function Oxide thickness UFDG-based search and 2D TCAD validation n Compact merged series-parallel logic gates n Novel dual-V th logic gates n New opportunities for FinFET-based design n Leakage power control Underlap as a design parameter

22 Double gate devices n Reduction in relative strength of gate n Two gates bring more electrostatic stability n Double gate devices have: Less DIBL, GIDL and leakage power Better I on /I off Better subthreshold slope Fabrication issues (alignment, etc) 22

23 FinFET n FinFETs are folded channel MOSFETs Easy manufacturing process Narrow vertical fin(s) stick up from the surface [1] D. Hisamoto, et al, FinFETA Self-Aligned Double-Gate MOSFET Scalable to 20nm, IEEE Tran on Electron Devices 23 [1]

24 FinFET cross view n Can you see the underlap? n Channel engineering unfeasible n Different strength for each gates is possible by tuning: Work–function Oxide thickness 24 Front Gate Back Gate Source n+ Channel-Undoped Drain p+ T ox T si Length

25 Outline n Introduction and motivation n Device characteristics n Circuit innovation with FinFET and results n Future directions and conclusion 25

26 I-V curves (current vs. drain voltage) n NMOS 26 n PMOS I ds V ds On-Current Off-current

27 Backgate and discrete width n Disabling the backgate: An order of magnitude less on-current Less static leakage Suitable for off-critical paths n The height cannot be changed across chip Stronger devices by adding parallel fins [1] Gate sizing will be a discrete problem W = n.H fin n=1,2,… [1] J. P. Colinge, FinFET and other multi-gate transistors, chapter 1 and 7, Springer, 08 27

28 DC properties n No dopant in channel: No random dopant fluctuations No Coulomb scattering => Higher mobility n Higher concentration of traps Higher flicker noise and noise figure n Due to 3D structure Much higher heat transmission resistance Danger of thermal runaway [1] Performance degrades less in alleviated temperatures [1] J. H. Choi, et al, The Effect of Process Variation on Device Temperature in FinFET circuits,

29 Analog devices n The unavoidable underlap Big source and drain resistance Less g m Less F T g m /2π(C gs +C gd ) Also due to new fringing capacitances Still better g m /g ds Good for gain of amplifiers n Not a very good SNR reported in ADCs and LCOs Due to high flicker noise and charge trapping 29

30 Sample RF circuit n Fast coupling of two independent gates can be exploited for building a compact low-power mixer A mixer for down converting the RF signal LO=1.8 GHz RF=1.6 GHz IF= =200Mhz Very good THD 30 FFT of Mixer Output

31 Outline n Introduction and motivation n Device characteristics n Circuit innovation with FinFET and results n Future directions and conclusion 31

32 Innovative circuit techniques n Disabling the backgate n Merging parallel transistors n Merging series transistors n A novel class of static logic 32

33 Disabling the backgate n Disabling backgate increases the threshold voltage Less leakage and slower Suitable for non-critical paths New gate has less C in, too Because the driver; sees less gates 33

34 Merging parallel transistors n If either of the gates is active; we still have a channel Works like an OR function [1] n Suitable for non-critical paths. Less static leakage and dynamic power (due to C in ) Higher sensitivity to parametric variation [1] V. Trivedi, et al, Physics-Based Compact Modeling for Nonclassical CMOS,

35 Merging series transistors n Series transistors can be merged if the transistor acts like an AND gate [1] It has low resistance; only if both of the inputs are active n Best design parameters chosen by SPICE simulation Oxide thickness and gate work-function tuning [1] M. Chiang, High-Density Reduced Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices, IEEE Tran On Electron Devices,

36 Why not use these ideas concurrently? 36

37 The main contributions n Rules for pull-down and pull-up network: Parallel structure=> series structure and vice versa. Weak type (AND-like) transistor => strong type (OR-like) and vice versa n No substrate effect in FinFET Transistors can be stacked in pull-up or pull-down network more easily Many more complex gates are possible! 37

38 New gate n Pull-down Boolean equation: PD = (a+b) * (c+d) n Pull-up Boolean equation: PU = (~a*~b) + (~c*~d) n PU and PD are complement Static logic n 24 different gates realized by just four transistors Just 3 Boolean functions with CMOS 38

39 Results n All the gates were simulated using UFDG model n The logical effort [1] model of each model was calculated n Technology libraries were constructed n ISCAS85 benchmarks were mapped n Addition of the new gates showed XX improvement in area YY improvement in power [1] R.F. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann,

40 Outline n Introduction and motivation n Device characteristics n Circuit innovation with FinFET and results n Future directions and conclusion 40

41 Conclusions n FinFET devices has a huge potential for replacing the planar CMOS technology n They have: Better Ion/Ioff ratios Better SCE suppression Possibility of a second independent gate n Innovative circuits were designed exploiting independent gate of FinFET n Savings in area and power consumptions observed 41

42 Future work n Near term: Completing the Synopsys chain Using backgate for performance tuning Offline/online Clustering? n Long term: SRAM Issue due to discrete width Design centering FinFET based RF circuits Amplifiers 42


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