Presentation on theme: "Novel dual-Vth independent-gate FinFET circuits"— Presentation transcript:
1 Novel dual-Vth independent-gate FinFET circuits Masoud Rostami and Kartik MohanramDepartment of Electrical and Computer EngineeringRice University, Houston, TX
2 Outline Introduction and motivation Background Dual-Vth independent-gate FinFETsLogic designSimulation resultsConclusions and future directions
3 Introduction Technology scaling Process variations Leakage power Short channel effectsPlanar double-gate FETs and FinFETsCompatibility with planar CMOSScalabilitySuppression of short channel effectsLow parametric variationsHigh Ion/IoffThe feature size of standard CMOS continues shrinking as predicted by Moore.Some of shortcomings of this technology are sensed more and more with advent of each new CMOS technology:There is a room for a new technology that addresses above issues; and the one which is based on previous one has a plus.
4 Motivation Conventional FinFETs Tied-gate devices Independent-gate FinFETsRemoving top oxideElectrically isolated, electrostatically coupled gatesMuttreja, Agarwal, and Jha, ICCD, 2007Caciki and Roy, IEEE TED, 2007Tawfik and Kursun, Microelectronics Journal, 2009
9 Background FinFET models University of Florida double-gate (UFDG) 9FinFET modelsUniversity of Florida double-gate (UFDG)Physics-based, good agreement with manufactured devicesFin height, silicon thickness, S/D doping, underlap, gate electrode work-functionPredictive technology model (PTM)Modeled as two parallel coupled SOI devicesUFDG MOSFET MODEL from SOI Group of university of Florida.Predictive Technology Model, from Arizona State University. (free).The former is a “Physical Model”, in contrast to prevalent “empirical models”. It has around 50 parameters instead of around 200 parameters of BSIM model.It takes the physical parameters of device (like height of fin, thickness of silicon, doping of S/D, length of underlap, etc)9
10 Background Finfet threshold voltage VT Φms and Cox tuning 10Finfet threshold voltage VTΦms and Cox tuningIndependent-gate FinFETsElectrically isolated, electrostatically coupledVth-dependence model [Colinge 2008]Vth-front = Vth-front0 – δ (Vgbs – Vth-back) if Vgbs < Vth-backVth-front = Vth-front0 in all other casesSubstrate-like effect in planar CMOSBy removing the top oxide; we can have independent mode operation; with higher routing and process costs.So, this backgate can be exploited like the substrate in planar technologies.10
11 Dual-Vth FinFETs Φms tuning Two additional mask steps Cox tuning through toxAsymmetric oxides [Masahara, IEEE EDL 2007]Device design using UFDG model
15 Dual-Vth FinFETs Good Vth separation Good noise margin (approx. 0.5Vdd)Leakage current in high-Vth devicepA for low-Vth devicesnA for high-Vth devices in disabled-gate modeComparable to 32nm CMOS
16 Dual-Vth logic gates Rules for pull-down and pull-up network: 16Rules for pull-down and pull-up network:Parallel structure ↔ series structure“Weak” AND-like high-Vth transistor ↔ “strong” OR-like low-Vth transistorDon’t start from a conventional gate (e.g. NAND2).The structure of pull-up network should be complement of the pull-down network.If “weak” type (AND-like) transistor is used inpull-down network, “strong” type (OR-like) should be used in pull-up network; and vise versa.There is no substrate effect in FinFET; because actually there is no substrate.Transistors can be stacked in pull-up or pull-down network more easily than CMOS.Considering the above points => So, many more complex gates are possible16
18 Novel dual-Vth logic gates Novel logic gatesIndependent back-gate as independent inputn-input gate with n, n+1, …, 2n inputsExample f = (a + b)(c + d)n = 2, 12 unique combinationsSome competitive, some notExponential in nOccupancy problemSeries-parallel graphsFunctionally equivalent,electrically different gates
19 Results Technology libraries for n = 3 Basic library Traditional INV, NAND, NOR, AOI, OAIPrevious work library = Basic library +Compact gate with parallel transistors mergedLow power gates with disabled back-gateMerged series = Previous work library +Dual-Vth logic gates, with series transistors merged as appropriateComplete library = Merged series library +Novel dual-Vth logic gates
20 Results ISCAS and OpenSPARC circuits Area (no. of fins), delay, total powerImprovements: Basic, Previous work, Merged seriesArea savings: 27%, 23%, 12%Delay improvement: 7%, 7%, 1%Total power: 24%, 21%, 15%Static power10-100X higher, but net contribution negligibleDynamic powerDominatesImprovements with proposed complete library significant
21 Conclusions Dual-Vth FinFET design Gate work-function Oxide thickness UFDG-based search and 2D TCAD validationCompact merged series-parallel logic gatesNovel dual-Vth logic gatesNew opportunities for FinFET-based designLeakage power controlUnderlap as a design parameter
22 Double gate devices Reduction in relative strength of gate Two gates bring more electrostatic stabilityDouble gate devices have:Less DIBL, GIDL and leakage powerBetter Ion/IoffBetter subthreshold slopeFabrication issues (alignment, etc)Gate’s length shrinkage has increased the “power” of drain electric field in respect to gate electric field.The idea is this: control channel from two sides with two gates.Double gate devices intrinsically have higher ability for combating drain impact:Early versions of double gate devices had manufacturing complications (source and drain alignment issues, etc)
23 FinFET FinFETs are folded channel MOSFETs Easy manufacturing process Narrow vertical fin(s) stick up from the surface D. Hisamoto, et al, “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20nm”, IEEE Tran on Electron Devices
24 FinFET cross view Can you see the underlap? Channel engineering unfeasibleDifferent strength for each gates is possible by tuning:Work–functionOxide thicknessFront GateToxSourcen+Channel-UndopedDrainp+TsiLengthBack Gate“Power” of both gates may be different. Each gate can have its own gate oxide thickness or work-function.
25 Outline Introduction and motivation Device characteristics Circuit innovation with FinFET and resultsFuture directions and conclusion
26 I-V curves (current vs. drain voltage) NMOSPMOSOff-currentOn-CurrentIdsIdsVdsVds
27 Backgate and discrete “width” Disabling the backgate:An order of magnitude less on-currentLess static leakageSuitable for off-critical pathsThe height cannot be changed across chipStronger devices by adding parallel fins Gate sizing will be a discrete problemW = n.Hfin n=1,2,… J. P. Colinge, “FinFET and other multi-gate transistors”, chapter 1 and 7, Springer, 08The height and width of device can NOT be changed across chip. Stronger devices can be obtained by adding parallel fins .
28 DC properties No dopant in channel: No random dopant fluctuations No Coulomb scattering => Higher mobilityHigher concentration of trapsHigher flicker noise and noise figureDue to 3D structureMuch higher heat transmission resistanceDanger of thermal runaway Performance degrades less in alleviated temperatures J. H. Choi, et al, “The Effect of Process Variation on Device Temperature in FinFET circuits”, 2007Heat transmission resistance is a order of magnitude less than planar.
29 Analog devices The unavoidable underlap Big source and drain resistanceLess gmLess FTgm/2π(Cgs+Cgd)Also due to new fringing capacitancesStill better gm/gdsGood for gain of amplifiersNot a very good SNR reported in ADCs and LCOsDue to high flicker noise and charge trappingThe unavoidable underlap results in a “huge” source and drain resistance. This has a huge toll on its analog properties:FT (the frequency that amplification has dropped to unity)
30 Sample RF circuitFast coupling of two independent gates can be exploited for building a compact low-power mixerA mixer for down converting the RF signalLO=1.8 GHzRF=1.6 GHzIF= =200MhzVery good THDFFT of Mixer Output
31 Outline Introduction and motivation Device characteristics Circuit innovation with FinFET and resultsFuture directions and conclusion
32 Innovative circuit techniques Disabling the backgateMerging parallel transistorsMerging series transistorsA novel class of static logic
33 Disabling the backgate Disabling backgate increases the threshold voltageLess leakage and slowerSuitable for non-critical pathsNew gate has less Cin, tooBecause the driver; sees less ‘gates’
34 Merging parallel transistors If either of the gates is active; we still have a channelWorks like an OR function Suitable for non-critical paths.Less static leakage and dynamic power (due to Cin)Higher sensitivity to parametric variation V. Trivedi, et al, “Physics-Based Compact Modeling for Nonclassical CMOS”,
35 Merging series transistors Series transistors can be merged if the transistor acts like an AND gate It has low resistance; only if both of the inputs are activeBest design parameters chosen by SPICE simulationOxide thickness and gate work-function tuning M. Chiang, “High-Density Reduced Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices”, IEEE Tran On Electron Devices, 2006
37 The main contributions Rules for pull-down and pull-up network:Parallel structure=> series structure and vice versa.“Weak” type (AND-like) transistor => “strong” type (OR-like) and vice versaNo substrate effect in FinFETTransistors can be stacked in pull-up or pull-down network more easilyMany more complex gates are possible!Don’t start from a conventional gate (e.g. NAND2).The structure of pull-up network should be complement of the pull-down network.If “weak” type (AND-like) transistor is used inpull-down network, “strong” type (OR-like) should be used in pull-up network; and vise versa.There is no substrate effect in FinFET; because actually there is no substrate.Transistors can be stacked in pull-up or pull-down network more easily than CMOS.Considering the above points => So, many more complex gates are possible
38 New gate Pull-down Boolean equation: PD = (a+b) * (c+d) Pull-up Boolean equation:PU = (~a*~b) + (~c*~d)PU and PD are complementStatic logic24 different gates realized by just four transistorsJust 3 Boolean functions with CMOS
39 Results All the gates were simulated using UFDG model The logical effort  model of each model was calculatedTechnology libraries were constructedISCAS85 benchmarks were mappedAddition of the new gates showedXX improvement in areaYY improvement in power R.F. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.
40 Outline Introduction and motivation Device characteristics Circuit innovation with FinFET and resultsFuture directions and conclusion
41 ConclusionsFinFET devices has a huge potential for replacing the planar CMOS technologyThey have:Better Ion/Ioff ratiosBetter SCE suppressionPossibility of a second independent gateInnovative circuits were designed exploiting independent gate of FinFETSavings in area and power consumptions observed
42 Future work Near term: Completing the Synopsys chain Using backgate for performance tuningOffline/onlineClustering?Long term:SRAMIssue due to discrete widthDesign centeringFinFET based RF circuitsAmplifiersGate’s widths in FinFET are quantized; this makes designing reliable and fast SRAM cells complicated. Design issues of FinFET-based SRAMs will be investigated in future projects.Is there any way for us to “cluster” the gates and apply a pre-specified voltage to each cluster? (i.e. finding fast and small cluster and applying an OPTIMIZED voltage to their corresponding backgate network, offline or online).