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CS1104: Computer Organisation Lecture 4: Logic Gates and Circuits

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1 CS1104: Computer Organisation Lecture 4: Logic Gates and Circuits

2 CS1104-4Lecture 4: Introduction to Logic Gates 2 Lecture 4: Logic Gates and Circuits Logic Gates The Inverter The AND Gate The OR Gate The NAND Gate The NOR Gate The XOR Gate The XNOR Gate Drawing Logic Circuit Analysing Logic Circuit Propagation Delay

3 CS1104-4Lecture 4: Introduction to Logic Gates 3 Lecture 4: Logic Gates and Circuits Universal Gates: NAND and NOR NAND Gate NOR Gate Implementation using NAND Gates Implementation using NOR Gates Implementation of SOP Expressions Implementation of POS Expressions Positive and Negative Logic Integrated Circuit Logic Families

4 CS1104-4Logic Gates4 Gate Symbols EXCLUSIVE OR abab a.b abab a+b aa' abab (a+b)' abab (a.b)' abab a b abab a.b & abab a+b 1 AND aa' 1 abab (a.b)' & abab (a+b)' 1 abab a b =1 OR NOT NAND NOR Symbol set 1 Symbol set 2 (ANSI/IEEE Standard )

5 CS1104-4Logic Gates: The Inverter5 The Inverter AA' A Application of the inverter: complement Binary number 1s Complement

6 CS1104-4Logic Gates: The AND Gate6 Logic Gates: The AND Gate (1/2) The AND Gate ABAB A.B & ABAB

7 CS1104-4Logic Gates: The AND Gate7 Logic Gates: The AND Gate (2/2) Application of the AND Gate 1 sec A Enable A Counter Reset to zero between Enable pulses Register, decode and frequency display

8 CS1104-4Logic Gates: The OR Gate8 The OR Gate 1 ABAB A+B ABAB

9 CS1104-4Logic Gates: The NAND Gate9 The NAND Gate & ABAB (A.B)' ABAB ABAB NAND Negative-OR

10 CS1104-4Logic Gates: The NOR Gate10 Logic Gates: The NOR Gate The NOR Gate NOR Negative-AND 1 ABAB (A+B)' ABAB (A+B)' ABAB

11 CS1104-4Logic Gates: The XOR Gate11 Logic Gates: The XOR Gate The XOR Gate =1 ABAB A B ABAB

12 CS1104-4Logic Gates: The XNOR Gate12 Logic Gates: The XNOR Gate The XNOR Gate ABAB (A B)' =1 ABAB (A B)'

13 CS1104-4Drawing Logic Circuit13 Drawing Logic Circuit (1/2) When a Boolean expression is provided, we can easily draw the logic circuit. Examples: (i) F1 = x.y.z' (note the use of a 3-input AND gate) x y z F1 z'

14 CS1104-4Drawing Logic Circuit14 Drawing Logic Circuit (2/2) (ii) F2 = x + y'.z (if we assume that variables and their complements are available) (iii) F3 = x.y' + x'.z x y' z F2 y'.z x' z F3 x'.z x.y' x y'

15 CS1104-4Quick Review Questions (1)15 Quick Review Questions (1) Textbook page 77. Questions 4-1, 4-2.

16 CS1104-4Analysing Logic Circuit16 Analysing Logic Circuit When a logic circuit is provided, we can analyse the circuit to obtain the logic expression. Example: What is the Boolean expression of F4? A'.B' A'.B'+C(A'.B'+C)' A' B' C F4 F4 = (A'.B'+C)' = (A+B).C'

17 CS1104-4Propagation Delay17 Propagation Delay (1/3) Every logic gate experiences some delay (though very small) in propagating signals forward. This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the output signal of the gate to change in response to changes in the input signals. Three different propagation delay times associated with a logic gate: t PHL : output changing from the High level to Low level t PLH : output changing from the Low level to High level t PD =(t PLH + t PHL )/2 (average propagation delay)

18 CS1104-4Propagation Delay18 Propagation Delay (2/3) InputOutput Input H L L H t PHL t PLH

19 CS1104-4Propagation Delay19 Propagation Delay (3/3) ABC Ideally, no delay: time Signal for C Signal for B Signal for A In reality, output signals normally lag behind input signals: time Signal for C Signal for B Signal for A

20 CS1104-4Calculation of Circuit Delays20 Calculation of Circuit Delays (1/3) Amount of propagation delay per gate depends on: (i) gate type (AND, OR, NOT, etc) (ii) transistor technology used (TTL,ECL,CMOS etc), (iii) miniaturisation (SSI, MSI, LSI, VLSI) To simplify matters, one can assume (i) an average delay time per gate, or (ii) an average delay time per gate-type. Propagation delay of logic circuit = longest time it takes for the input signal(s) to propagate to the output(s). = earliest time for output signal(s) to stabilise, given that input signals are stable at time 0.

21 CS1104-4Calculation of Circuit Delays21 Calculation of Circuit Delays (2/3) In general, given a logic gate with delay, t. If inputs are stable at times t 1,t 2,..,t n, respectively; then the earliest time in which the output will be stable is: max(t 1, t 2,.., t n ) + t Logic Gate t1t1 t2t2 tntn :: max (t 1, t 2,..., t n ) + t To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

22 CS1104-4Calculation of Circuit Delays22 Calculation of Circuit Delays (3/3) As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) where outputs S and C, experience delays of 2t and 3t, respectively. XYXY S C Z max(0,0)+t = t t max(t,0)+t = 2t max(t,2t)+t = 3t 2t

23 CS1104-4Quick Review Questions (2)23 Quick Review Questions (2) Textbook page 77. Questions 4-3 to 4-5.

24 CS1104-4Universal Gates: NAND and NOR24 Universal Gates: NAND and NOR AND/OR/NOT gates are sufficient for building any Boolean functions. We call the set {AND, OR, NOT} a complete set of logic. However, other gates are also used because: (i) usefulness (ii) economical on transistors (iii) self-sufficient NAND/NOR: economical, self-sufficient XOR: useful (e.g. parity bit generation)

25 CS1104-4NAND Gate25 NAND Gate (1/2) NAND gate is self-sufficient (can build any logic circuit with it). Therefore, {NAND} is also a complete set of logic. Can be used to implement AND/OR/NOT. Implementing an inverter using NAND gate: (x.x)' = x' (T1: idempotency) xx'

26 CS1104-4NAND Gate26 NAND Gate (2/2) ((x.y)'(x.y)')' = ((x.y)')' idempotency = (xy) involution ((x.x)'(y.y)')' = (x'.y')' idempotency = x''+y'' DeMorgan = x+y involution Implementing AND using NAND gates: Implementing OR using NAND gates: x x.y y (x.y)' x x+y y x' y'

27 CS1104-4NOR Gate27 NOR Gate (1/2) NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic Can be used to implement AND/OR/NOT. Implementing an inverter using NOR gate: (x+x)' = x' (T1: idempotency) xx'

28 CS1104-4NOR Gate28 NOR Gate (2/2) ((x+x)'+(y+y)')'=(x'+y')' idempotency = x''.y'' DeMorgan = x.y involution ((x+y)'+(x+y)')' = ((x+y)')' idempotency = (x+y) involution Implementing AND using NOR gates: Implementing OR using NOR gates: x x+y y (x+y)' x x.y y x' y'

29 CS1104-4Implementation using NAND gates 29 Implementation using NAND gates (1/2) Possible to implement any Boolean expression using NAND gates. Procedure: (i) Obtain sum-of-products Boolean expression: e.g. F3 = x.y'+x'.z (ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates e.g. F3 = x.y'+x'.z = (x.y'+x'.z)' ' involution = ((x.y')'. (x'.z)')' DeMorgan

30 CS1104-4Implementation using NAND gates 30 Implementation using NAND gates (2/2) F3 = ((x.y')'.(x'.z)') ' = x.y' + x'.z x' z F3 (x'.z)' (x.y')' x y'

31 CS1104-4Implementation using NOR gates31 Implementation using NOR gates (1/2) Possible to implement any Boolean expression using NOR gates. Procedure: (i) Obtain product-of-sums Boolean expression: e.g. F6 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates. e.g. F6 = (x+y').(x'+z) = ((x+y').(x'+z))' ' involution = ((x+y')'+(x'+z)')' DeMorgan

32 CS1104-4Implementation using NOR gates32 Implementation using NOR gates (2/2) F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z) x' z F6 (x'+z)' (x+y')' x y'

33 CS1104-4Implementation of SOP Expressions 33 Implementation of SOP Expressions (1/2) Sum-of-Products expressions can be implemented using: 2-level AND-OR logic circuits 2-level NAND logic circuits AND-OR logic circuit F = A.B + C.D + E F A B D C E

34 CS1104-4Implementation of SOP Expressions 34 Implementation of SOP Expressions (2/2) NAND-NAND circuit (by circuit transformation) a) add double bubbles b) change OR-with- inverted-inputs to NAND & bubbles at inputs to their complements F A B D C E A B D C E' F

35 CS1104-4Implementation of POS Expressions 35 Implementation of POS Expressions (1/2) Product-of-Sums expressions can be implemented using: 2-level OR-AND logic circuits 2-level NOR logic circuits OR-AND logic circuit G = (A+B).(C+D).E G A B D C E

36 CS1104-4Implementation of POS Expressions 36 Implementation of POS Expressions (2/2) NOR-NOR circuit (by circuit transformation): a) add double bubbles b) changed AND-with- inverted-inputs to NOR & bubbles at inputs to their complements G A B D C E A B D C E' G

37 CS1104-4Quick Review Questions (3)37 Quick Review Questions (3) Textbook page 77. Questions 4-6 to 4-8.

38 CS1104-4Positive & Negative Logic38 Positive & Negative Logic (1/3) In logic gates, usually: H (high voltage, 5V) = 1 L (low voltage, 0V) = 0 This convention is known as positive logic. However, the reverse convention, negative logic possible: H (high voltage) = 0 L (low voltage) = 1 Depending on convention, same gate may denote different Boolean function.

39 CS1104-4Positive & Negative Logic39 Positive & Negative Logic (2/3) A signal that is set to logic 1 is said to be asserted, or active, or true. A signal that is set to logic 0 is said to be deasserted, or negated, or false. Active-high signal names are usually written in uncomplemented form. Active-low signal names are usually written in complemented form.

40 CS1104-4Positive & Negative Logic40 Positive & Negative Logic (3/3) Positive logic: Negative logic: Enable Active High: 0: Disabled 1: Enabled Enable Active Low: 0: Enabled 1: Disabled

41 CS1104-4Integrated Circuit Logic Families41 Integrated Circuit Logic Families (1/2) Some digital integrated circuit families: TTL, CMOS, ECL. TTL: Transistor-Transistor Logic. Uses bipolar junction transistors Consists of a series of logic circuits: standard TTL, low-power TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky TTL, etc.

42 CS1104-4Integrated Circuit Logic Families42 Integrated Circuit Logic Families (2/2) CMOS: Complementary Metal-Oxide Semiconductor. Uses field-effect transistors ECL: Emitter Coupled Logic. Uses bipolar circuit technology. Has fastest switching speed but high power consumption. Performance characteristics Propagation delay time. Power dissipation. Fan-out: Fan-out of a gate is the maximum number of inputs that the gate can drive. Speed-power product (SPP): product of the propagation delay time and the power dissipation.

43 CS1104-4Summary43 Summary Logic Gates AND, OR, NOT NAND NOR Drawing Logic Circuit Analysing Logic Circuit Given a Boolean expression, draw the circuit. Given a circuit, find the function. Implementation of a Boolean expression using these Universal gates. Implementation of SOP and POS Expressions Positive and Negative Logic Concept of Minterm and Maxterm

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