3 Drawbacks of Metal-gate MOS Transistors Metal-gate PMOS transistors cannot maintain the minimal(+0.5V) threshold variation.Excess surface state charges and mobile ion contamination are two main sources of threshold variation.Suffer from excessive overlap capacitance.Parasitic capacitances Cgs and Cgd slow the transistor because they must be charged and discharged during switching.Aluminum is used as gate material which can erode completely causing contact spiking.
4 Features of Polysilicon-gate CMOS Process Consists of nine masking stepsOptimized to form complementary PMOS and NMOS transistors on a common substrateCan also fabricate some analog circuits with slight modificationsUse (100) silicon to reduce surface state density and improve threshold voltage controlPolysilicon-gate is doped with phosphorus to minimize mobile ion contamination, resulting in faster switching speeds and better control of threshold voltage
5 Oveview of Polysilicon-gate CMOS Process Start with P-substrateGrow P-type epitaxial layer on the substrateCreate N-well regions and channel stop regionsGrow gate oxide (thin oxide) and field oxide (thick oxide)Deposit and pattern polysilicon layerImplant source and drain regions, substrate contactsCreate contact windows, deposit and pattern metal layer
6 Epitaxial GrowthP-type substrate is doped with as much boron as possible to minimize substrate resistivityLightly doped P-type epitaxial layer is grown on substrateNMOS transistors are formed directly on the epi layer which serves as a backgateP-epiP-substrate
7 N-well DiffusionThe wafer is then oxidized and etched to open windows through which ion implantation deposits a controlled dose of phosphorusA prolonged drive creates a deep lightly doped N-type region called N-wellThermal oxidation covers the exposed silicon with thin layer of pad oxide
8 N-well DiffusionIn N-well CMOS process, NMOS transistors occupy the epi and PMOS transistors reside in well. This process optimizes NMOS at the expense of PMOSpad oxideP-epiN-wellP-substrate
9 P-well DiffusionP-well CMOS process uses N+ substrate and N- epitaxial layer and a P-well. NMOS transistors are formed in P-well and PMOS transistors in the epi. This process optimizes PMOS at the expense of NMOSpad oxideN-epiP-wellN-substrate
10 Why N-well CMOS Process? The N-well process offers a slightly better NMOS transistor than P-well CMOS and also allows the use of a grounded substrate favored by most circuit designers.In a P-well process the NMOS still outperforms its counterpart because electrons are more mobile than holes
11 Inverse MoatLOCOS process is used to define field regions and moat regionsLocally oxidized regions of the die are called ‘field regions’Areas protected from oxidation are called ‘moat regions’First a patterned nitride layer is formed by depositing nitride across entire wafer
12 Inverse Moat (cont.)A selective etch is used to remove nitride over the field regionsThe photomask used is called inverse moat mask because it codes for areas where moat is absentphotoresistnitridepad oxideP-epiN-wellP-substrate
13 Channel Stop ImplantsChannel stop implants are required to ensure that thick-field threshold exceed the operating voltagesIt uses a boron implant followed by a patterned phosphorus implantPhosphorus implant counterdopes boron implant and raises NMOS thick-field threshold above maximum operating voltage
14 Channel Stop Implants (cont.) After LOCOS oxidation, a suitable etching strips away the remnants of the nitride block maskCurved transition region at the edges of moat results from oxidants diffusing under the edges of nitride film and is called ‘bird’s-beak’All photoresist is stripped off from the wafer in preparation for LOCOS oxidation
15 Channel Stop Implants (cont.) A thin layer of oxide called ‘dummy gate oxide’ is grown in moat regions to eliminate any nitride formed underneath the pad oxide due to ‘kooi effect’photoresistBoron channel stopPhosphorus channel stopnitridepad oxideP-epiN-wellP-substrate
16 Threshold AdjustMethod 1: Two separate implants to set PMOS Vt and NMOS Vt. This Method allows independent optimization of both thresholdsMethod 2: Single Vt adjust implant to simultaneously reduce PMOS threshold and increase NMOS threshold
17 Threshold Adjust (cont.) The boron Vt adjust implant penetrates of the dummy gate oxide to dope underlying siliconAfter the Vt adjust implant, dummy gate oxide is stripped away to reveal bare silicon in moat regionsDummy gate oxideBoron channel stopPhosphorus channel stopField oxideP-epiN-wellP-substrateBoron Vt adjust implant
18 Polysilicon Deposition and Patterning Polysilicon layer used to form gate electrodes is heavily doped with phosphorus to reduce its resistivityThe deposited polysilicon layer is patterned using polymaskGate oxidepolyBoron channel stopPhosphorus channel stopField oxideP-epiN-wellP-substrateBoron Vt adjust implant
19 Source/Drain Implants NSD implant involves application of photoresist to the wafer, followed by patternig using the NSD maskHeavily doped N-types regions are formed by implanting ardenic through exposed gate oxidePhotoresist residue is stripped off and a new photoresist layer is patterned using PSD mask
20 Source/Drain Implants (cont.) Heavily doped P-type region is formed by implanting Boron through exposed gate oxidePhotoresist is again stripped off and a brief anneal activates the implanted dopantsGate oxidepolyPSDNSDField oxideP-epiN-wellP-substrate
21 ContactsMLO (Multilevel Oxide) is deposited and the wafer is again coated with photoresistContact windows are created and silicide is formed in the contact openingsThin film of refractory metal precedes a much thicker layer of copper doped aluminium
22 Protective OvercoatProtective overcoat is deposited over the final layer of metallization to provide mechanical protection and to prevent contamination of the dieSelected areas of metallization are etched to attach bondwires to the integrated circuit
35 Process ExtensionCMOS process extension tend to focus on improving the PMOS and NMOS transistors.Types:- One set seeks to provide higher operating voltages.- Another focuses on reducing the size of the transistor.
36 Process Extension Double-level Metal -It adds two steps to the process: one vias andOne for metal-2Interlevel oxide(ILO) is deposited between theTwo metal layers-This provides insulation-The planarization improves for the secondLevel
37 Process Extension Double-level Metal(cont.) The extra processing steps increase the cost of the wafer.Use of extra metal layers would reduce the area required for interconnection in high density auto routed logic.
38 Process Extension Double-level Metal(cont.) Advantages of more levels of metal interconnect,2,3,4,etc:-Eases automated routing and improves power and clock distribution to modules.-Vias are used to connect upper layers of metal to metal 1.-”Contact cuts” are made from metal 1 to diffusion or poly.
40 Process Exention Silicidation Silicidation: an anneal(sintering) resulting in the formation metal-Si alloy to act as a contact.Used for:1.Reducing sheet resistance.-Poly resistances between 20 and 40 ohms.-Silicide (silicon and tantalum) used as gate material, between 1 and 5 ohms.-Can be extended to source and drain, called.salicide.
42 Process Extension Lightly Doped Drain Transistors Designed to minimize hot-carriee effects; The reduced doping gradient between drain and channel lower electric field.Implementation: typical NMOS with 3mm length operate within 5-10V, PMOS with the same dimensions can withstand V. That’s where the LDD comes in handy.LDD can withstand substantially higher drain-to-source voltage than the singly doped drain (SDD)devices.
43 Process Extension LDD(cont.) Use of two drain diffusions:-One forming a lightly doped drift region near the edge of the gate.-The other forming a more heavily doped region beneath the contact, this will reduce the drain resistance of the structure and allows the transistor to retain most of the performance of a conventional SDD device.
44 Process Extension LDD(cont.) Process to form LDD transistors:Use of an oxide sidewall spacer to self-align the two drain diffusions, therefore, enabling precise control of the width of the drift region.
45 Process Extension LDD(cont.) Fabrication steps:A shallow implant self-aligned to the edges of the gate polysilicon deposits the lightly doped drain.The wafer is coated with a thick layer of isotropically deposited oxide.Use anisotropic dry etch to remove most of the deposited oxide.A second drain implant self-aligned to the edges of the oxide sidewall spacers to form the heavily doped portions of the LDD.
46 Process Extension LDD(cont.) Advantages:Improves tolerability of high drain-to-source voltages.Does not increase real-estate needed.Provides greater depletion regions widths, which in turn, provides better tolerances to hot carrier degradation.
47 Process Extension LDD(cont.) Drawbacks:Requires additional masks to selectively block N-S/D implantsSlightly increases drawn channel lengths(0.5-1m)
48 Extended-drain, High-voltage Transistors Potentially can withstand in excess of 30 V.Uses existing masks of standard n-well poly-CMOS process.Drawbacks:-Inherently long channel devices.-High overlap capacitance.-Asymmetric.-Higher susceptibility to oxide rupture( decreases device transconductance).