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EE 4345 Semiconductor Electronics Design Project CMOS Process Mohammad Butt Ahmad ElmardiniDevices Heithem Souissi Dina Miqdadi Process Extension Fares.

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Presentation on theme: "EE 4345 Semiconductor Electronics Design Project CMOS Process Mohammad Butt Ahmad ElmardiniDevices Heithem Souissi Dina Miqdadi Process Extension Fares."— Presentation transcript:

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2 EE 4345 Semiconductor Electronics Design Project CMOS Process Mohammad Butt Ahmad ElmardiniDevices Heithem Souissi Dina Miqdadi Process Extension Fares Alnajjar Wyatt Sullivan

3 CMOS Process

4 Drawbacks of Metal-gate MOS Transistors Metal-gate PMOS transistors cannot maintain the minimal(+0.5V) threshold variation. Excess surface state charges and mobile ion contamination are two main sources of threshold variation. Suffer from excessive overlap capacitance. Parasitic capacitances C gs and C gd slow the transistor because they must be charged and discharged during switching. Aluminum is used as gate material which can erode completely causing contact spiking.

5 Features of Polysilicon-gate CMOS Process Consists of nine masking steps Optimized to form complementary PMOS and NMOS transistors on a common substrate Can also fabricate some analog circuits with slight modifications Use (100) silicon to reduce surface state density and improve threshold voltage control Polysilicon-gate is doped with phosphorus to minimize mobile ion contamination, resulting in faster switching speeds and better control of threshold voltage

6 Oveview of Polysilicon-gate CMOS Process Start with P-substrate Grow P-type epitaxial layer on the substrate Create N-well regions and channel stop regions Grow gate oxide (thin oxide) and field oxide (thick oxide) Deposit and pattern polysilicon layer Implant source and drain regions, substrate contacts Create contact windows, deposit and pattern metal layer

7 Epitaxial Growth P-type substrate is doped with as much boron as possible to minimize substrate resistivity Lightly doped P-type epitaxial layer is grown on substrate NMOS transistors are formed directly on the epi layer which serves as a backgate P-epi P-substrate

8 N-well Diffusion The wafer is then oxidized and etched to open windows through which ion implantation deposits a controlled dose of phosphorus A prolonged drive creates a deep lightly doped N-type region called N-well Thermal oxidation covers the exposed silicon with thin layer of pad oxide

9 N-well Diffusion In N-well CMOS process, NMOS transistors occupy the epi and PMOS transistors reside in well. This process optimizes NMOS at the expense of PMOS P-epi P-substrate pad oxide N-well

10 P-well Diffusion P-well CMOS process uses N+ substrate and N- epitaxial layer and a P-well. NMOS transistors are formed in P-well and PMOS transistors in the epi. This process optimizes PMOS at the expense of NMOS N-epi N-substrate P-well pad oxide

11 Why N-well CMOS Process? The N-well process offers a slightly better NMOS transistor than P-well CMOS and also allows the use of a grounded substrate favored by most circuit designers. In a P-well process the NMOS still outperforms its counterpart because electrons are more mobile than holes

12 Inverse Moat LOCOS process is used to define field regions and moat regions Locally oxidized regions of the die are called field regions Areas protected from oxidation are called moat regions First a patterned nitride layer is formed by depositing nitride across entire wafer

13 Inverse Moat (cont.) A selective etch is used to remove nitride over the field regions The photomask used is called inverse moat mask because it codes for areas where moat is absent P-epi P-substrate N-well pad oxide photoresist nitride

14 Channel Stop Implants Channel stop implants are required to ensure that thick-field threshold exceed the operating voltages It uses a boron implant followed by a patterned phosphorus implant Phosphorus implant counterdopes boron implant and raises NMOS thick-field threshold above maximum operating voltage

15 Channel Stop Implants (cont.) After LOCOS oxidation, a suitable etching strips away the remnants of the nitride block mask Curved transition region at the edges of moat results from oxidants diffusing under the edges of nitride film and is called birds-beak All photoresist is stripped off from the wafer in preparation for LOCOS oxidation

16 Channel Stop Implants (cont.) A thin layer of oxide called dummy gate oxide is grown in moat regions to eliminate any nitride formed underneath the pad oxide due to kooi effect P-epi P-substrate N-well pad oxide nitride photoresist Boron channel stopPhosphorus channel stop

17 Threshold Adjust Method 1: Method 1: Two separate implants to set PMOS V t and NMOS V t. This Method allows independent optimization of both thresholds Method 2: Method 2: Single V t adjust implant to simultaneously reduce PMOS threshold and increase NMOS threshold

18 Threshold Adjust (cont.) The boron V t adjust implant penetrates of the dummy gate oxide to dope underlying silicon After the V t adjust implant, dummy gate oxide is stripped away to reveal bare silicon in moat regions P-epi P-substrate N-well Boron channel stopPhosphorus channel stop Field oxide Dummy gate oxide Boron Vt adjust implant

19 Polysilicon Deposition and Patterning Polysilicon layer used to form gate electrodes is heavily doped with phosphorus to reduce its resistivity The deposited polysilicon layer is patterned using polymask P-epi P-substrate N-well Boron channel stopPhosphorus channel stop Field oxide Gate oxide Boron Vt adjust implant poly

20 Source/Drain Implants NSD implant involves application of photoresist to the wafer, followed by patternig using the NSD mask Heavily doped N-types regions are formed by implanting ardenic through exposed gate oxide Photoresist residue is stripped off and a new photoresist layer is patterned using PSD mask

21 Source/Drain Implants (cont.) Heavily doped P-type region is formed by implanting Boron through exposed gate oxide Photoresist is again stripped off and a brief anneal activates the implanted dopants P-epi P-substrate N-well Field oxide Gate oxide poly NSD PSD

22 Contacts MLO (Multilevel Oxide) is deposited and the wafer is again coated with photoresist Contact windows are created and silicide is formed in the contact openings Thin film of refractory metal precedes a much thicker layer of copper doped aluminium

23 Protective Overcoat Protective overcoat is deposited over the final layer of metallization to provide mechanical protection and to prevent contamination of the die Selected areas of metallization are etched to attach bondwires to the integrated circuit

24 Devices

25 Transistor structure

26 Transistor (Bell Labs)

27 Transistor Layout

28 Gate Voltage and The Channel

29 Basic Transistor Parasitic

30 P-Channel MOSFET

31 N-Channel MOSFET

32 Layout and cross section of PNP substrate transistor

33 PSD/NSD Resistors

34 MOSFET Capacitances capacitances have three origins: –The basic MOS structure –The channel charge –The pn-junctions depletion regions

35 Process Extension

36 CMOS process extension tend to focus on improving the PMOS and NMOS transistors. Types: - One set seeks to provide higher operating voltages. - Another focuses on reducing the size of the transistor.

37 Process Extension Double-level Metal -It adds two steps to the process: one vias and One for metal-2 Interlevel oxide(ILO) is deposited between the Two metal layers -This provides insulation -The planarization improves for the second Level

38 Process Extension Double-level Metal(cont.) Process extension. The extra processing steps increase the cost of the wafer. Use of extra metal layers would reduce the area required for interconnection in high density auto routed logic.

39 Process Extension Double-level Metal(cont.) Advantages of more levels of metal interconnect,2,3,4,etc: -Eases automated routing and improves power and clock distribution to modules. -Vias are used to connect upper layers of metal to metal 1. -Contact cuts are made from metal 1 to diffusion or poly.

40 Process Extension Double-level Metal(cont.)

41 Process Exention Silicidation Silicidation: an anneal(sintering) resulting in the formation metal-Si alloy to act as a contact. Used for: 1.Reducing sheet resistance. -Poly resistances between 20 and 40 ohms. -Silicide (silicon and tantalum) used as gate material, between 1 and 5 ohms. -Can be extended to source and drain, called. salicide.

42 Process Extension Silicidation(cont.)

43 Process Extension Lightly Doped Drain Transistors Designed to minimize hot-carriee effects; The reduced doping gradient between drain and channel lower electric field. Implementation: typical NMOS with 3mm length operate within 5-10V, PMOS with the same dimensions can withstand 15-20 V. Thats where the LDD comes in handy. LDD can withstand substantially higher drain-to- source voltage than the singly doped drain (SDD)devices.

44 Process Extension LDD(cont.) Use of two drain diffusions: -One forming a lightly doped drift region near the edge of the gate. -The other forming a more heavily doped region beneath the contact, this will reduce the drain resistance of the structure and allows the transistor to retain most of the performance of a conventional SDD device.

45 Process Extension LDD(cont.) Process to form LDD transistors: Use of an oxide sidewall spacer to self- align the two drain diffusions, therefore, enabling precise control of the width of the drift region.

46 Process Extension LDD(cont.) Fabrication steps: 1. A shallow implant self-aligned to the edges of the gate polysilicon deposits the lightly doped drain. 2. The wafer is coated with a thick layer of isotropically deposited oxide. 3. Use anisotropic dry etch to remove most of the deposited oxide. 4. A second drain implant self-aligned to the edges of the oxide sidewall spacers to form the heavily doped portions of the LDD.

47 Process Extension LDD(cont.) Advantages: Improves tolerability of high drain-to- source voltages. Does not increase real-estate needed. Provides greater depletion regions widths, which in turn, provides better tolerances to hot carrier degradation.

48 Process Extension LDD(cont.) Drawbacks: Requires additional masks to selectively block N-S/D implants Slightly increases drawn channel lengths(0.5-1 m)

49 Extended-drain, High-voltage Transistors Potentially can withstand in excess of 30 V. Uses existing masks of standard n-well poly- CMOS process. Drawbacks: -Inherently long channel devices. -High overlap capacitance. -Asymmetric. -Higher susceptibility to oxide rupture( decreases device transconductance).

50 Extended-drain, High-voltage Transistors

51 Extended-Drain, High- voltage(cont).

52 Extended-Drain, High Voltage(cont).

53 References The Art of Analog Layout, by Alan Hastings Semiconductorglossary.com http://www.iue.tuwien.ac.at/publications/PhD %20Theses/puchner/node36.html http://www.iue.tuwien.ac.at/publications/PhD %20Theses/puchner/node36.html http://www.sse.uu.se/education/acad/pdf/2000 /Design_Rules.pdf http://www.sse.uu.se/education/acad/pdf/2000 /Design_Rules.pdf http://vlsi.wpi.edu/webcourse/ch02/ch02.html


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