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1 EECS 465: Digital Systems Design Lecture Notes Logic Design Using Compound Components: Multiplexers SHANTANU DUTT Department of Electrical and Computer Science University of Illinois, Chicago Phone: (312) ; URL:

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2 The World of Integrated Circuits (LSI/VLSI) Full-Custom ASICs Semi-Custom ASICs User Programmable FPGA PLD PLA/PALCPLDs Simple gates (nand/ nor/xor/xnor..) Complex gates/cells Muxes PLA/PAL (layout aspect; not programmable)

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3 Logic Design Using Multiplexers A Transmission Gate ( T-Gate ) A Out In=B Steering gate. When A=1, In is Steered to Out. [I.e., the T-gate conducts] Thus Out = B when A=1 Out = AB Symbolic for T-gate: OutIn A is the control input (CI) Normal CI connected to A Bubbled CI connected to T-gate conducts when A=1. A

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4 Reversing the connection of A: A bubble CI normal CI OutIn A T-gate conducts when A=0. Multiplexer (MUX) Design: A 2:1 MUX. Out S S Z I0I0 I1I1 I0I0 I1I1 2:1 MUX Z S Z= I 0 when S=0 Z= I 1 when S=1

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5 Generalization of the TT: S Z S Z S Z 1 0 = S S Z 0 I 0 1 I 1 is the function implemented by the above 2:1 MUX. Such a TT in general provides a decomposition of the final function Z into constituent functions I 0 & I 1 Thus, the 2:1 MUX can also be implemented by logic gates: 2:1 MUX : z I0I0 S I1I1

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6 I1I1 2:1 MUX Z S0S0 I0I0 A 2:1 MUX selects input I i if S 0 = I [If S 0 = 0, Z = I 0 S 0 = 1, Z = I 1 ] 4:1 MUX I0I0 I1I1 I2I2 I3I3 Z S1S1 S0S0 The same can be said about a 4:1 MUX: Input I i is selected (Z=I i ) if S 1 S 0 combination represents the number i in binary.

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7 In general, # of data inputs (I i s) is 2 n # of control I/Ps = n [If S 1 S 0 = 00 (#0), Z = I o S 1 S 0 = 01 (#1), Z = I 1 S 1 S 0 = 10 (#2), Z = I 2 S 1 S 0 = 11 (#3), Z = I 3 ] S 1 S 0 Z 0 0 I I I I 3 A generalized or symbolic TT

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8 2 n : 1 S n-1 S1S1 S0S0 Z I1I1 I0I0 In general for a 2 n :1 MUX with control signals/inputs S n-1 ··· S 1 S 0 & data inputs I 0, ···,, Z = I i when S n-1 ··· S 1 S 0 combination represents #i in binary.

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9 Saw the design of a 2:1 MUX using T-gates, as well as logic gates Messy and expensive to design larger MUXes using a flat TT based approach A 4:1 MUX can be hierarchically constructed using 2:1 MUXes Idea: Divide the selection problem by bits of the select/control variables LSB of control variables 4:1 MUX I0I0 I1I1 I2I2 I3I3 Z S0S0 S1S1 Design of MUXes using Divide-&-Conquer Inputs selected are those w/ the same lsb or S 0 values. So further selection needs to be based on the non-lsb bits. I1I1 2:1 MUX S0S0 I0I0 I3I3 2:1 MUX S0S0 I2I2 2:1 MUX Z S1S1 MSB These inputs should have different lsb or S 0 values, since their sel. is based on S 0. All other bits should be equal. These inputs should have different lsb or S 0 values, since their sel. is based on S 0. All other bits should be equal.

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10 When S 0 =0, I 0, I 2 get selected at the 1st level, i.e., Input w/ 0 in LSB. When S 0 =1, I 1, I 3 (LSB=1) get selected at the 1st level. If S 0 = 0, I 0, I 2, become the 0th & 1st inputs to the next level. At the next level, the I/P order # is determined by the rest of the bits of their index after stripping off the LSB. Thus I 0 I 0 I 2 I 1 At level (# 0) 1 0 (# 2) strip away for the 2nd level inputs.

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11 I0I2I0I2 S 0 =0 From level 1 I0I1I0I1 Level 2 Z= I 0 of level 2 (I 0 of level 1), S 1 =0. = I 1 of level 2 (I 2 of level1) if S 1 =1. I1I3I1I3 Level strip 1 strip S 0 =1 I0I1I0I1 2:1 MUX Z S1S1 Z= I 0 of Level 2 (I 1 of Level1) if S 1 =0 = I 1 of level 2 (I 3 of level 1) if S 1 =1 Thus the design works as a 4:1 MUX.

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12 8:1 MUX I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 S 2 S 1 S 0 An 8:1 MUX is designed similarly. I1I1 2:1 MUX S0S0 I0I0 I3I3 2:1 MUX S0S0 I2I2 I5I5 S0S0 I4I4 I7I7 2:1 MUX S0S0 I6I6 2:1 MUX 4:1 MUX S2S2 S1S1 I0I0 I2I2 I4I4 I6I6 Z I1I1 I3I3 I5I5 I7I7 Selected when S 0 = 1 Selected when S 0 = 0 Z These inputs should have different lsb or S 0 values, since their sel. is based on S 0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.

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13 8:1 MUX I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 S 2 S 1 S 0 Opening up the 8:1 MUXs hierarchical design I1I1 2:1 MUX S0S0 I0I0 I3I3 2:1 MUX S0S0 I2I2 I5I5 S0S0 I4I4 I7I7 2:1 MUX S0S0 I6I6 2:1 MUX I0I0 I2I2 I4I4 I6I6 Z 2:1 MUX 2:1 MUX 2:1 MUX Z S1S1 S1S1 S2S2 I2I2 I6I6 I6I6 Selected when S 0 = 0 Selected when S 0 = 0, S 1 = 1. These i/ps should differ in S 2 Selected when S 0 = 0, S 1 = 1, S 2 =1 These inputs should have different lsb or S 0 values, since their sel. is based on S 0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. These inputs should have different S 1 values, since their sel. is based on S 1 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level.

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14 8:1 MUX I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 S 2 S 1 S 0 8:1 MUXs: Input groupings for a different control variable order (S 2, S 0, S 1 ) I4I4 2:1 MUX S2S2 I0I0 I5I5 2:1 MUX S2S2 I1I1 I6I6 S2S2 I2I2 I7I7 2:1 MUX S2S2 I3I3 2:1 MUX I4I4 I5I5 I6I6 I7I7 Z 2:1 MUX 2:1 MUX 2:1 MUX Z S0S0 S0S0 S1S1 I4I4 I6I6 I6I6 Selected when S 2 = 1 Selected when S 2 = 1, S 0 = 0. These i/ps should differ in S 1 Selected when S 0 = 0, S 1 = 1, S 2 =1 These inputs should have different lsb or S 2 values, since their sel. is based on S 2 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. These inputs should have different S 0 values, since their sel. is based on S 0 (all other remaining, i.e., unselected bit values should be the same). Similarly for other i/p pairs at 2:1 Muxes at this level. +/- bit 2 +/- bit 0 +/- bit 1 Seed input

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15 General D&C/Hierarchical Design of a 2 n :1 MUX First select inputs based on S 0, using 2 n-1 2:1 Muxes; 2 n-1 inputs get selected on 2 n-1 lines The problem now reduces to that of a 2 n-1 :1 Mux Continue recursively (to a 2 n-2 :1, 2 n-3 :1, …., 4:1, 2:1 Mux design problems) until the final output is obtained. Cost = 2 n -1 2:1 Muxes = 6*(2 n -1) gate inputs (6 is the gate-i/p cost of a 2:1 Mux) Compare to flat design: (n+1)*2 n + 2 n = (n+2)*2 n gate inputs (will actually require more for n > 4, as large gates required for a 2-level impl. are not desirable (e.g., driving resistance become too large). More expensive for n > 4 (for 2-level design, if at all that is possible), and even more expensive for a multi-level design. Note that both costs are exp. in n, but linear in the # of inputs (2 n ), which is the important parameter. More realistic hardware cost (complexity in terms of gate i/ps) for flat deign when up to only 4-i/p gates are avail? For simplicity, assume n is a power of 4. Design Strategy: 2:1 S n-1 S1S1 2 n-1 :1 MUX 2 n :1 MUX I0I0 S n-1 S 0 S0S0 S0S0 S0S0 2 n-1 2:1 MUXes

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16 Using MUXes to Realize Logic Circuits Example: -- Use A,B,C as control inputs to an 8:1 MUX. -- Treat the data inputs I 0, ···, I 7 as possible minterms of f: Input I i is a minterm if #i appears in the m notation of f. If I i is a minterm of f, it should be connected to a 1, otherwise it should be connected to a 0. I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 8:1 MUX S 2 S 1 S 0 A B C f

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17 A 3-variable function can always be implemented by only an 8:1 MUX. Interestingly, a 3-var. function can also always be implemented by only a 4:1 MUX (assuming vars & their complements are avail.). Note: Can represent a function in terms of all combinations of amy subset of variables. E.g., any f (A,B,C) = AB(I 0 ) + AB(I 1 ) + AB(I 2 ) + AB (I 3 ), where the I j s can be 0, 1, C or C generalization of Shannons expansion theorem: f(X) = xi*f(X,xi=1) + xi*f(X,xi=0) Example f(A,B,C) = m(0,2,6,7) Can determine I j s using a K-Map: Select any 2 variables, say, A,B, for the 2 control inputs In a 3-var. K-map, group together squares into 2-squares in which the other variable C varies, but A,B remains constant. Form implicants only within 2-squares and write out the function as sum of a min. of these implicants (choosing essential implicants first, etc.) AB C 2-squares

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18 The function now is in terms of combinations of A, B ANDed with either C,, 1, or 0 Connect either C,, 1, 0 to the appropriate data input corresponding to the A,B combination they are ANDed with in the expression for f. Thus Note: 0 is ANDed with an A,B combination (e.g., above) when the 2-square corresponding to that combination does not have any 1s, i.e., when none of the product terms obtained from the K-map in the above manner has that combination of A, B in them. Note that a 4:1 MUX implements the function Thus for the above f, and

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:1 MUX S 1 S 0 f A B 0101 A B f A general n-variable function f(A n-1, A n-2, ···, A 0 ) Implementation possible using a 2 n : 1 MUX (w/o requiring any extra gates)? Yes. Implementation possible using a 2 n-1 : 1 MUX (w/o requiring any extra gates) ? Yes (assuming complemented variables are available). Corresponding generalized TT

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20 AB CD A B C f E.g.: A 4-var. function f(A,B,C,D) Choose A, B, C as the control inputs

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21 -- In general, a 2 i : 1 MUX, where i < n-1, can be used to implement an n-var. function f(A n-1,,A 0 ) by choosing any i variables, say, A i-1,, A 0 ( This is just an example of i variables; you can choose any i of the n variables) as the control inputs of the MUX. However, for i < n-1, extra logic gates may be required. Where is a function of A n-1,,A i that ANDs with the k th product term of variables A i-1,, A 0 that represents the binary # k, -- Express f in terms of all combinations of A i-1,, A 0 (using Shannons expansion recursively i times for each of these vars in turn) as:

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22 Thus we get the implementation: The trick is to choose the right i variables so that the total # of logic gates needed for the g k s is minimum (thus us a hard problem but interesting and beneficial to choose). Where each g k may need extra logic gates for its implementation. 2 i :1 MUX A i-1 A 0 g 0 (A n-1,···, A i+1 ) I0I0

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23 Heuristic Technique for gate-minimized design of a n-var. function using a 2 i :1 MUX: PIs can only be formed within each groups of squares in which the control vars. are constant (constant areas), which are 4-squares in the example below. To min. # of gates, choose the i control vars such that the largest-size implicants & the smallest # of them can be formed in its set const. areas. Main idea of how to achieve this: Form all PIs in the full K-map, and choose the constant areas that break as few of the EPIs as possible, and then as few of the obvious choices of other PIs as possible Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just like in a full K-Map (i.e., for all PIs in each area, determine and select all EPIs in that area, cover remaining MTs in that area by the least-cost set of the remaining PIs). AB CD AB CD a b b c c d d dd BD const. (blue) AB CD d d c c a b AD const. (maroon) AB CD AC const. (green)CD const. (orange) Example : 4-var. function f(A,B,C,D) ; n=4. Let i=2 For i=2 (2 control variables from A,B,C,D for a 4:1 MUX), the K-map needs to be partitioned into groups of 4-squares, such that within each 4-square the 2 control variables are constant. EPIs

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24 A study of the 1s in the above K-map tells us that this is achieved by the set of 4-squares that are the columns of the K-map, i.e., for control variables A, B. Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just like in a full K-Map (i.e., for all PIs in each area, determine and select all EPIs in that area, cover remaining MTs in that area by the least-cost set of the remaining PIs). We this obtain: A B :1 MUX S 1 S 0 f C 0 Implementation: No logic gates needed! (NOTE: This will not always be the case) 4-squares where A,B = constant A,B are the mux control vars. AB CD a b c c d d BC const. (yellow) AB CD AB const. (lt. green)

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25 AB CD If we choose A,C as the control variables (which also cut 0 EPIs), then the 4-squares w/ constant A, C are: Grouping 1s only within the 4-squares, we get 4 terms and : all are essential (within their constant areas)

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26 -- We thus obtain f in terms of all combinations of A, C as I0I0 I1I1 I2I2 I3I :1 MUX S 1 S 0 f A C B 0 -- Thus choosing A,C as control variables, results in 2 extra 2 i/p gates (gate i/p cost = 4) compared to choosing A, B, for which the cost = 0.

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