# W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Physical Limitations of Logic Gates – Week 10a In a computer.

## Presentation on theme: "W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Physical Limitations of Logic Gates – Week 10a In a computer."— Presentation transcript:

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Physical Limitations of Logic Gates – Week 10a In a computer well have circuits of logic gates to perform specific functions Computer Datapath: Boolean algebraic functions using binary variables Symbolic representation of functions using logic gates Example: D C A B Every node has capacitance and interconnects have resistance. It takes time to charge these capacitances. Thus, output of all circuits, including logic gates is delayed from input. For example we will define the unit gate delay

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California UNIT GATE DELAY D Time delay D occurs between input and output: computation is not instantaneous Value of input at t = 0 + determines value of output at later time t = D A B C 0 1 1 0 Logic State t t D 0 0 Input (A and B tied together) Output

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California UNIT GATE DELAY D in ASYNCHRONOUS LOGIC Time delay D is measured from the last input change A B C 0 1 1 0 Logic State t t D 0 0 Input B Output Input A

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Synchronous and Asynchronous Logic Time delay occurs between input and output in real logic circuits. Therefore the time at which output appears is difficult to predict… it depends for example on how many gates you go through. A B C Thus in the modified gate, C will be valid precisely one gate delay ( D ) after the clock input CK, goes high (A and B are evaluated precisely when CK goes high, what they do before or after this is irrelevant; CK must go low, then high again before the NAND gate again looks at A and B). CK To make logic operations as fast as possible, we need predictability of signal availability. That is we want to know exactly when C is correctly computed from A and B. This requirement argues for synchronous logic, in which a clock signal CK actually initiates the computation of C. We will often not distinguish asynchronous vs synchronous logic.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California EFFECT OF GATE DELAY Cascade of Logic Gates A B C D Inputs have different delays, but we ascribe a single worst-case delay D to every gate How many gate delays for shortest path?ANSWER : 2 How many gate delays for longest path?ANSWER : 3 Which path is the important one?ANSWER : LONGEST

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California D t t t t t Logic state D D D 2 D 0 3 D D TIMING DIAGRAMS Show transitions of variables vs time A B C Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. No change at t = 3 D Note becomes valid one gate delay after B switches

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Note that the specific voltage range for 0 or 1 depends on logic family, and in general decreases with logic generations Specific voltage ranges correspond to 0 or 1 Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is v IN (t), output is v OUT (t) inside a large system t V in (t)

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Approximation D GATE DELAY (PROPAGATION DELAY) Define as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V. Inverters are designed so that the gate delay is symmetrical (rise and fall) V in (t) t 1.5 V out (t) t 1.5 D D

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: if clock frequency = 500 MHz clock period = (5 10 8 s 1 ) 1 Period = 2 10 9 s = 2 ns (nanoseconds) Gate delay must be D = (1/35) Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3 10 8 m/s Distance traveled in 57 ps is: C X D = (3x10 8 m/s)(57x10 -12s ) = 17 x 10 -4 m = 1.7cm

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California WHAT DETERMINES GATE DELAY? The delay is mostly simply the charging of the capacitors at internal nodes. We already know how to analyze this.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Example The gate delay is simply the charging of the capacitors at internal nodes. Oversimplified example using ideal inverter, II and 5V logic swing 2.5 5 RC = 0.1ns so 0.069ns after v IN switches by 5V, Vx moves 2.5V t v IN 2.5 5 Vx D = 0.069ns v OUT II R C Vx RC = 0.1ns MODEL

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Simple model for logic delays Model actual logic gate as an ideal logic gate fed by an RC network which represents the dominant R and C in the gate. )t(v IN t v IN VXVX D = 0. 69 RC v OUT R C Ideal Logic gate Actual Logic Gate Ideal Logic gate t VXVX )t(v OUT etc.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California How can we build inverters, NAND gates, etc. ? We need some sort of controlled switch: that is a device in which a switch opens or closes in response to an input voltage (a control voltage). If we have a controlled switch it is an easy matter to build inverters, NAND gates, etc. For example an electromagnetic relay has a coil producing a magnetic field causing some contacts to snap shut when a voltage is applied to the coil. Lets imagine a simple controlled switch, but include in it some resistance (all real devices have non-zero resistance).

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Controlled Switch Model The basic idea: We need a switch which is controlled by an input voltage. For example: Input V = 0 means the switch is open, whereas an input voltage of 2V means that the switch is closed (We will call this a Type N controlled switch) V Input Output R + - + - I Input high IOutput I vs. V Input low

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Controlled Switch Model Now lets combine these switches to make an inverter. - Type N controlled switch means switch is closed if input is high. (V G > V S ) Type P controlled switch means switch is closed if input is low. (V G < V S ) Output S Input RPRP - + + - + - G Output RNRN + + - + - G S

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Controlled Switch Model of Inverter So if V IN is 2V then S N is closed and S P is open. Hence V OUT is zero. Input Output RNRN - + S P is closed if V IN < V DD RPRP - + + - + - V DD = 2V V SS = 0V SNSN SPSP S N is closed if V IN > V SS V IN V OUT But if V IN is 0V then S P is closed and S N is open. Hence V OUT is 2V.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Controlled Switch Model of Inverter IF V IN is 2V then S N is closed and S P is open. Hence V OUT is zero (but driven through resistance R N ). RNRN + - - V DD = 2V V SS = 0V V IN =2V V OUT But if V IN is 0V then S P is closed and S N is open. Hence V OUT is 2V (but driven through resistance R P ). + - - V DD = 2V V SS = 0V V IN =0V RPRP V OUT

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California V IN jumps from 0V to 2V Controlled Switch Model of Inverter IF there is a capacitance at the output node (there always is) then V OUT responds to a change in V IN with our usual exponential form. V OUT t V IN jumps from 2V to 0V RNRN + - - V DD = 2V V SS = 0V V IN =2V V OUT + - - V DD = 2V V SS = 0V V IN =0V RPRP V OUT

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Controlled Switch Model of Inverter We will expand on this model in coming weeks. The controlled switches will of course be MOS transistors. The resistance will be the effective output resistance of the MOS devices. The capacitance will be the input capacitance of the MOS devices. But now lets briefly review the energy used in charging and discharging capacitances so we can start to estimate chip power.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEW Capacitor initially uncharged (Q=CV DD at end) Switch moves @ t=0 Energy out of "battery" This must be difference of E and E C, i.e. 2 DD CV 2 1 CASE 1- Charging i V DD t=0 R C RDRD Energy into R (heat) Power out of "battery" Power into R Power into C 0 CC dtiVE 2 DD CV 2 1 Energy into C

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California ENERGY AND POWER IN CHARGING Capacitor initially uncharged (Q=CV DD at end) Switch moves @ t=0 Energy out of "battery" 2 DD CV 2 1 Energy into R (heat) 2 DD CV 2 1 Energy into C V DD t=0 R C RDRD In charging a capacitor from a fixed voltage source V DD half the energy from the source is delivered to the capacitor, and half is lost to the charging resistance, independent of the value of R.

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS Capacitor initially charged (Q=CV DD ) and discharges. Switch moves @ t=0 Energy out of battery This must be energy initially in C, i.e. 2 DD CV 2 1 CASE 2- discharging i V DD t=0 R C RDRD Energy into R D (heat) Power out of battery Power into R D Power out of C 0 CC dtiVE 2 DD CV 2 1 Energy out of C =0 Power in/out of R =0

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California ENERGY IN DISCHARGING CAPACITORS Capacitor initially charged (Q=CV DD ) and discharges. Switch moves @ t=0 2 DD CV 2 1 V DD t=0 R C RDRD Energy into R D (heat) 2 DD CV 2 1 Energy out of C When a capacitor is discharged into a resistor the energy originally stored in the capacitor (1/2 CV DD 2 ) is dissipated as heat in the resistor

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Each node transition (i.e. charging or discharging) results in a loss of (1/2)(C)(V DD ) 2 How many transitions occur per second? Well if the node is pulsed up then down at a frequency f (like a clock frequency) then we have 2f dissipation events. POWER DISSIPATION in DIGITAL CIRCUITS A system of N nodes being pulsed at a frequency f to a signal voltage V DD will dissipate energy equal to (N) (2f )(½CV DD 2 ) each second Therefore the average power dissipation is (N) (f )(CV DD 2 )

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California LOGIC POWER DISSIPATION Power = (Number of gates) x (Energy per cycle) x (frequency) N = 10 7 ; V DD = 2 V; node capacitance = 10 fF; f = 10 9 s -1 (1GHz) P = 400 W! -- a toaster! Pretty high but realistic What to do? (N increases, f increases, hmm) 1)Lower V DD 2)Turn off the clock to the inactive nodes Clever architecture and design! Lets define as the fraction of nodes that are clocked (active). Then we have a new formula for power. P = (N) (CV DD 2 ) (f )

W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California LOGIC POWER DISSIPATION with power mitigation Power = (Energy per transition) x (Number of gates) x (frequency) x fraction of gates that are active ( ). In the last 5 years V DD has been lowered from 5V to about 1.5V. It cannot go very much lower. But with clever design, we can make as low as 1 or 10%. That is we do not clock those parts of the chip where there is no computation being made at the moment. Thus the 400W example becomes 4 to 40W, a manageable range (4W with heat sink, 40W with heat sink plus fan on the chip). P = N f CV DD 2 Heat pipe – can be Used to remove heat From an IC better than A copper heat conductor IC Hot IC Cu rod Hollow heat pipe

Download ppt "W. G. Oldham EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California Physical Limitations of Logic Gates – Week 10a In a computer."

Similar presentations