# Lab 08: SR Flip Flop Fundamentals:

## Presentation on theme: "Lab 08: SR Flip Flop Fundamentals:"— Presentation transcript:

Lab 08: SR Flip Flop Fundamentals:
Slide 2 NOR Gate SR Flip Flop. Slide 3 SR Flip Flop. Slide 4 SR Flip Flop with a positive edge clock: Slide 5 SR Flip Flop with a negative edge clock: Slide 6 Flip Flop waveform diagrams:

Lab 08: NOR Gate SR Flip Flop :
The cross-coupled NOR gates creates an SR Flip Flop. Flip Flops are the basic elements used in computer memory. The S input is called Set. The R input is called Reset. 1 1 Q R S Q settles at logic 0 S R Output 1 1 1 1 1 1 1 Q changes from 1 to 0. Called the reset mode! No Change Q stays at 0 Both outputs settle to 0. This breaks the definition. This condition is not allowed Q changes from 0 to 1. Called the Set mode! Reset: Q changes to 0 Set: Q changes to 1 1 1 1 1 1 1 1 Ambiguous : Not allowed! Output Q and Q are by definition always opposite to each other. If Q=1 then Q =0. Behaviour Table: Logic gates are defined by Truth Tables. Flip Flops are defined by behaviour tables. Two different names for tables that do essentially the same job. To generate the behaviour table you must assume an initial condition at output Q. This is necessary because the outputs are wired to the inputs. This creates a feedback path that can only be analyzed when a starting point is assumed. Start with S,R = 0,0 : The analysis procedure works as follows: 1-Place the initial conditions at output Q on the diagram. Assume Q =0. 2-Place the input conditions at S and R. 3-Analyze the top NOR gate and record Q. 4-Analyze the bottom NOR gate and record Q. 5-Repeat steps 3 and 4 until Q and Q settle. Next S,R = 0,1 : The analysis procedure works as follows: 1-Place the initial conditions at output Q on the diagram. Assume Q =1. 2-Place the input conditions at S and R. 3-Analyze the top NOR gate and record Q. 4-Analyze the bottom NOR gate and record Q. 5-Repeat steps 3 and 4 until Q and Q settle. Next S,R = 1,1 : The analysis procedure works as follows: 1-Place the initial conditions at output Q on the diagram. Assume Q =0. 2-Place the input conditions at S and R. 3-Analyze the top NOR gate and record Q. 4-Analyze the bottom NOR gate and record Q. 5-Repeat steps 3 and 4 until Q and Q settle. Next S,R = 1,0 : The analysis procedure works as follows: 1-Place the initial conditions at output Q on the diagram. Assume Q =0. 2-Place the input conditions at S and R. 3-Analyze the top NOR gate and record Q. 4-Analyze the bottom NOR gate and record Q. 5-Repeat steps 3 and 4 until Q and Q settle. Slide #2

Lab 08: SR Flip Flop : Cross-coupled NOR gates create an SR Flip Flop. It is easy to remember the operation of an SR flip flop using only the symbol without repeatedly analyzing the cross coupled NOR gate system. The S input is called SET the R input is called reset. They are both active high. Active high means that S =1 sets the flip flop (S =0 does not set). R =1 resets the flip flop (R =0 does not reset). SET means set output Q to “1”. RESET means reset output Q to “0”. S R Q 1 S=1 : Set Mode : 1 R=1 : reset Mode : : Hold Mode : 1 R=1 : reset Mode : 1 S=1 : Set Mode : : Hold Mode : 1 Assume Q starts at 0. 1 reset : Q =0. 1 Output SETs : Q =1. 1 reset : Q =0. 1 Output SETs : Q =1. 1 Q does not change 1 Q does not change Symbol When S =0 and R =0 then Q does not change. Q holds its logic level (1 or 0). It is equivalent to not issuing either the set or the reset command. When S =1 and R =1 then Q is ambiguous. Both Q and Q outputs go to the same logic level which breaks the definition of a flip flop. You can think of it this way … S =1 says SET and R =1 says reset. The flip flop does not know whether the output should be Q =1 or Q =0. S=R=1 should never be used! There is a second variety of SR flip flop that uses an active low S and R inputs. The internal system is cross coupled NAND gates. Active low means that S =0 sets the flip flop (S =1 does not set). R =0 resets the flip flop (R =1 does not reset). When S =1 and R =1 then Q does not change. Q holds its logic level (1 or 0). It is equivalent to not issuing either the set or the reset command. 1 S=0 : Set Mode : S R Q 1 : HOLD Mode : 1 R=0 :reset Mode : 1 Q does not change 1 Output SETs : Q =1. 1 Assume Q starts at 0. 1 Output SETs : Q =1. When S =0 and R =0 then Q is ambiguous. The flip flop does not know whether the output should be Q =1 or Q =0. S=R=0 should never be used! Slide #3

SR Flip Flop with edge triggered clock
Lab 08: SR Flip Flop with a Positive Edge Triggered Clock Input : A Positive EDGE triggered flip flop has a new input called clock. The clock requires a transition from 0 to 1 in order that S and R controls output Q. Holding a constant logic 1 or a constant logic 0 at the clock input does not allow SR to change output Q. An edge triggered clock is identified with “>Clk” on the symbol. S R Q >Clk 1 S=1 : Set Mode : 1 Output SETs : Q =1. 1 Assume Q starts at 0. A transition from 0 to 1 at “>Clk” is required in order for the flip flop to respond to S and R. This is called a” Positive Edge”. Watch the animation to see how you would set the flip flop. Holding “>Clk” at logic 1 will not result in S and R controlling Q. Only the 0 to 1 transition at “>Clk“ causes the output Q to change. SR Flip Flop with edge triggered clock Inside the SR Flip Flop with Positive Edge Triggered Clock: The clock signal is applied to the input. >Clk S R Q 1/0 1 3 2 The NOT gate delays the signal because it has a propagation delay. Propagation delay is the reaction time of the inverter. Let’s use 3 to 10 nanoSec. 3 to 10 nanoSec delay. During the 3 to 10 nanoSec interval, AND gate #1 outputs a 1. AND gates #2 and #3 transfer the logic levels to internal SR and Q responds. After the 3 to 10 nanoSec interval AND gate #1 outputs a 0. AND gates #2 and #3 transfer the logic 0 to internal SR and Q holds(S=R=0 is Hold mode). To re-clock the flip flop you need another positive edge. Clock must return to 0 and re-change back to 1. Slide #4

SR Flip Flop with edge triggered clock
Lab 08: SR Flip Flop with a Negative Edge Triggered Clock Input : A negative edge triggered flip flop requires a transition from 1 to 0 at at the clock input in order for the flip flop to respond to S and R. This is called a” Negative Edge”. It is the opposite of a positive edge triggered flip flop. An edge triggered clock is identified with “o|>Clk” on the symbol. S R Q >Clk 1 S=1 : Set Mode : 1 Output SETs : Q =1. 1 Assume Q starts at 0. Watch the animation to see how you would set the flip flop. Holding “o|>Clk” at logic 0 will not result in S and R controlling Q. Only the 1 to 0 transition at “o|>Clk“ causes the output Q to change. SR Flip Flop with edge triggered clock Here is a summary of the flip flop devices S and R control the response at Q continuously. S and R control the response at Q only when Clk is making a transition. On the edge of the clock signal. S R Q Non-Clocked SR S R Q >Clk Edge Triggered Slide #5

Set Reset Clock Note Pack 5 : Flip Flop Waveform Diagrams :
To draw waveforms for flip flops you need to begin with an initial condition at Q, mark the area where the clock input is asserted and then draw the output response. Let’s use an initial condition of Q =0. The initial condition Q =0 is marked as a dot on the output waveform diagram. Set Reset Clock S R Q >Clk The flip flop has a negative edge triggered clock. The clock is asserted when Clk makes a transition from 1 to 0. The asserted zone is marked off in yellow. Analyze the waveform and draw Q. On this negative edge S=1 and R=0: SET Mode. Thus Q sets to 1. No analysis is required until the next negative edge. On this negative edge S=R=0: No Change Mode. Thus Q holds at 0. No analysis is required until next negative edge. Until the clock changes from 1 to 0 it is NOT asserted. Thus Q holds at 0. Slide #6