3 80386DX Features Flexible 32-Bit Microprocessor 8, 16, 32-Bit Data Types8 General Purpose 32-Bit RegistersVery Large Address Space4 Gigabyte Physical64 Terabyte Virtual4 Gigabyte Maximum Segment Size
4 Contd. Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging4 Levels of ProtectionVirtual 8086 Mode Allows Running of Software in a Protected and Paged SystemOptimized for System PerformancePipelined Instruction ExecutionOn-Chip Address Translation Caches20, 25 and 33 MHz Clock
5 Previous members in x86 family No Memory Management UnitApplication program size limited to available memory (RAM)Single tasking environmentSegment size maximum 64KB
6 Requirements of Efficient working Environment MultitaskingProtection –Restricted Access to Data , Code & StackSecure Access to I/O devicesWith minimum available memory, execution of application of any size
7 Modes of OperationReal Address ModeProtected ModeVirtual 86 Mode
8 Protected Mode Features MultitaskingProtectionVirtual Memory- Demand Paging
9 Significant Facts Microprocessor can execute one instruction at a time Microprocessor works very fast ( in microseconds ) compared to human response time
11 Components of MMUSegmentation Unit : Deals with segments of a program .Paging Unit : Divides programs in fixed size (4KB) blocks.
12 Segmentation UnitDefines various types of segments with different attributes and provides segment level protection.Cannot be Disabled.It converts Logical Address to Linear Address.
13 Paging Unit Divides a program in fixed sized pages(4KB). Swaps pages between RAM & secondary device as required.Provides page level protection.It converts Linear address to Physical address.Optional -can be enabled or disabled.
14 Address Translation Virtual / logical address to Linear Address CS : IP Base address + IP Linear addressLinear Address to Physical AddressLinear Address Base address from page table + offset
15 Segmentation Segmentation is one method of memory management. Segmentation provides the basis for protection.Segments are used to encapsulate regions ofmemory which have common attributes.Segment selectors can be considered the logical “name” of a program module or data structure
16 What Are Segments?Segments are variable sized blocks of linear addresses which have certain attributes associated with themThere are two main types of ( non system) segments: code and dataSegments are of variable size - as smallas 1 byte or as large as 4 gigabytesBase address (32bit) + Offset (32bit) Linear AddressBase address defined in the descriptor by system
17 A segment is described by a structure – Segment Descriptor Each segment (Code/data/stack) has a unique descriptor in memoryAll descriptors are maintained in a table – Descriptor Table
25 Global Descriptor Table The Global Descriptor Table (GDT) contains descriptors which are possibly available to all of the tasks in a system.The GDT can contain any type of segment descriptor except for descriptors which areused for servicing interrupts (i.e. interrupt and trap descriptors).Every Intel386 DX system contains a GDT
26 Contd. Generally the GDT contains code and data segments used by the operating systems and task state segments, and descriptors for the LDTs in a system.GDT contains descriptors for segments whichare common to all tasks
27 Local Descriptor Table LDTs contain descriptors which are associated with a given task.Generally, operating systems are designedso that each task has a separate LDT.The LDT may contain only code, data, stack, task gate, and call gate descriptors.There can be 0 or many LDTs.
28 LDTRThe visible portion of the LDT register contains only a 16-bit selector.This selector refers to a Local Descriptor Table descriptor in the GDT.LDTs provide a mechanism for isolating a given task's code and data segments from the rest of the operating system
33 Privilege Level Privilege Level-One of the four hierarchical privilege levels.Level 0 is the most privileged level and level 3 is the least privileged.More privileged levels are numerically smaller than less privileged levels.
34 Privileged Instructions System tables are manipulated by the operating system.Therefore, the load descriptor table instructions are privileged instructions.The instructions that can be executed at CPL=0 are privileged instructions.
36 PagingPaging is another type of memory management useful for virtual memory multitasking operating systemsFreed space of an outgoing task always same as that needed for an incoming taskA page most likely corresponds to only a portion of a module or data structure
37 Components of the paging mechanism The page directoryThe page tablesThe page itself (page frame)
38 AdvantagesA uniform size of 4KB for all of the elements simplifies memory allocation and reallocationschemes, since there is no problem with memory fragmentation.Protection can further be increased at page level.
39 Linear Address to Physical Address Index to DirectoryIndex to TableOffset in Page4KB pageDirectory EntryPage Table EntryBase addressPagePDBRCR3Page Table DirectoryPage Table
41 PAGE DESCRIPTOR BASE REGISTER CR3 is the Page Directory Physical Base Address Register. It contains the physical starting address of the Page Directory.Page Directory is always page aligned.CR2 is the Page Fault Linear Address register. It holds the 32-bit linear address which caused the last page fault detected
42 PAGE DIRECTORYThe Page Directory is 4K bytes long and allows up to 1024 Page Directory Entries.Each Page Directory Entry contains the address of the next level of tables, the Page Tables and information about the page table.Page Directory Entry points to Page Table
44 PAGE TABLESEach Page Table is 4K bytes and holds up to Page Table Entries.Page Table Entries contain the starting address of the page frame and statistical information about the pagePage tables can be shared between tasks and swapped to disks.
46 Page Level ProtectionThe paging mechanism distinguishes between two levels of protection: User which corresponds to level 3 of the segmentation based protection, and supervisor which encompasses all of the other protection levels (0, 1, 2).Programs executing at Level 0, 1 or 2 bypass the page protection, although segmentation based protection is still enforced by the hardware.
47 Bits used for Protection The U/S and R/W bits are used to provideUser/Supervisor and Read/Write protection for individual pages or for all pages covered by a Page Table Directory EntryThe U/S and R/W bits in the first level Page Directory Table apply to all pages describedby the page table pointed to by that directoryentry.
48 Page Level ProtectionThe U/S and R/W bits in the second level Page Table Entry apply only to the page described by that entry.The U/S and R/W bits for a given page are obtained by taking the most restrictive ofthe U/S and R/W from the Page Directory Table Entries and the Page Table Entries
49 Translation Lookaside Buffer Performance would degrade substantiallyif the processor was required to access twolevels of tables for every memory reference.Intel386 DX keeps a cache of the most recently accessed pages, this cache is called theTranslation Lookaside Buffer (TLB).
50 Translation Lookaside Buffer The TLB is a four-way set associative 32- entry page table cache.It automatically keeps the most commonly used Page Table Entries in the processor.The 32-entry TLB coupled with a 4K page size, results in coverage of 128K bytes of memory addresses.
52 TLB HitThe paging unit hardware receives a 32-bit linear address from the segmentation unit.The upper 20 linear address bits are compared with all 32 entries in the TLB to determine if there is a match.If there is a match (i.e. a TLB hit), then the 32-bit physical address is calculated and will be placed on the address bus.
53 TLB MissIntel386 DX will read the appropriate Page Directory Entry. If P = 1 on the Page Directory Entry indicating that the page table is in memory, then the Intel386 DX will read the appropriate Page Table Entry