Presentation on theme: "Multilevel Page Tables"— Presentation transcript:
1 10.4.4 Multilevel Page Tables Q1. What is a page table? What is the input and output of a page table?Q2. Is there a page table for each process?Q3. How many entries are there in a page table if the top 10 bits of a virtual address are designated for a page number?Multilevel page tablesSystem can store in noncontiguous locations in main memory those portions of process’s page table that the process is usingHierarchy of page tablesEach level containing a table that stores pointers to tables in the level belowBottom-most level comprised of tables containing address translationsCan reduce memory overhead compared to direct-mapping system
3 10.4.2 Paging Address Translation by Associative Mapping Maintaining entire page table in cache memory is often not viableDue to cost of high-speed, location-addressed cache memory and relatively large size of programsIncrease performance of dynamic address translationPlace entire page table into content-addressed associative memoryEvery entry in associative memory is searched simultaneouslyContent-addressed cache memory is also prohibitively expensive
4 10.4.2 Paging Address Translation by Associative Mapping Figure Paging address translation with pure associative mapping.
5 10.4.3 Paging Address Translation with Direct/Associative Mapping Compromise between cost and performanceMost PTEs are stored in direct-mapped tables in main memoryMost-recently-used PTEs are stored in high-speed set-associative cache memory called a Translation Lookaside Buffer (TLB)If PTE is not found in TLB, the DAT mechanism searches the table in main memoryCan yield high performance with relatively small TLB due to localityA page referenced by a process recently is likely to be referenced again soonQ: Is there a piece of hardware involved here?
6 Figure 10.14 Paging address translation with combined associative/direct mapping.
7 10.4.5 Inverted Page Tables Inverted page tables One inverted page table stores one PTE in memory for each page frame in the systemInverted relative to traditional page tablesUses hash functions to map virtual page to inverted page table entry
8 Figure 10.16 Page address translation using inverted page tables.
9 Inverted Page TablesHashing can lead to collisions which increase address translation time by increasing the number of times memory must be accessedCollisions can be reduced by increasing the range of the hash functionCannot increase the size of the inverted page table because it must store exactly one PTE for each page frameHash anchor table (HAT) increases the range of the hash function by adding another level of indirectionSize must be carefully chosen to balance table fragmentation and performance
10 Figure 10.17 Inverted page table using a hash anchor table. Inverted Page TablesFigure Inverted page table using a hash anchor table.
11 10.4.6 Sharing in a Paging System Sharing in multiprogramming systemsReduces memory consumed by programs that use common data and/or instructionsRequires system identify each page as sharable or non-sharable
12 10.5 SegmentationSegmentBlock of program’s data and/or instructionsContains meaningful portion of the program (e.g. procedure, array, stack)Consists of contiguous locationsSegments need not be the same size nor must they be adjacent to one another in main memoryA process may execute while its current instructions and referenced data are in segments in main memory
13 10.5.1 Segmentation Address Translation by Direct Mapping Process references a virtual memory address v = (s, d)DAT adds the process’s segment map table base address, b, to referenced segment number, sb + s forms the main memory address of the segment map table entry for segment sSystem adds s´ to the displacement, d, to form real address, r
14 10.5.1 Segmentation Address Translation by Direct Mapping Figure Virtual address translation in a pure segmentation system.
15 10.5.1 Segmentation Address Translation by Direct Mapping Segment map table entryIndicates that segment s starts at real memory address s´Contains a resident bit to indicate if segment is in memoryIf so, it stores the segment base addressOtherwise, it stores the location of the segment on secondary storageAlso contains a length field that indicates the size of the segmentCan be used to prevent a process from referencing addresses outside the segment
16 10.5.3 Protection and Access Control in Segmentation Systems Protection bits are added to the segment map table entry and checked when a process references an addressIf the segment is not in memory, a segment-missing fault is generatedIf d > l, a segment-overflow exception is generatedIf the operation (e.g., read, write, execute, append) is not allowed, a segment-protection exception is generated
17 3. Comment on the idea of associative mapping using TLB. Group Discussion 10 4/9/20091. Suppose that the allocation of the virtual address is as the following. The upper 20 bits are for page number and the lower 12 bits are for displacement or offset. What is the page size in this system? How large is the page table in terms of the number of entries?2(a). What is the advantage of using multi-level page tables over using a single-level page table?2(b). What is the disadvantage of using multi-level page tables over using a single-level page table?3. Comment on the idea of associative mapping using TLB.4. What are the pros and cons for an inverted page table verses a regular page table?
18 10.6 Segmentation/Paging Systems Segments occupy one or more pagesAll pages of segment need not be in main memory at oncePages contiguous in virtual memory need not be contiguous in main memoryVirtual memory address implemented as ordered triple v = (s, p, d)s is segment numberp is page number within segmentd is displacement within page at which desired item located
19 10.6.1 Dynamic Address Translation in a Segmentation/Paging System Figure Virtual address translation with combined associative/direct mapping in a segmentation/paging system.
20 10.6.1 Dynamic Address Translation in a Segmentation/Paging System Figure Table structure for a segmentation/paging system.