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EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalization/Compensation of Transmission Media Channel (copper or fiber) 1.

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Presentation on theme: "EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalization/Compensation of Transmission Media Channel (copper or fiber) 1."— Presentation transcript:

1 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalization/Compensation of Transmission Media Channel (copper or fiber) 1

2 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Optical Receiver Block Diagram O E LACDREQDMUX -18 dBm 10 mV p-p 10 µA 400 mV p-p TIA 2

3 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Copper Cable Model Copper Cable Where: L is the cable length a is a cable-dependent characteristic 4-foot cable 15-foot cable 2

4 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Effect of Copper on Broadband Data waveformeye diagram 3

5 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Adaptive Analog Equalizer for Copper Implemented in Jazz Semiconductor SiGe BiCMOS process: 120 GHz f T npn 0.35 µm CMOS 4

6 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalizer Block Diagram 5

7 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Analog Equalizer Concept (1) 1 C1C1 111 V1V1 V2V2 V3V3 1 simple channel modelbandpass filtercombined flat response + peaked response Simple linear circuit (normalized to 1Hz): s 6

8 EECS 270C / Winter 2014Prof. M. Green / UC Irvine V1V1 V2V2 1 C1C1 111 V1V1 V2V2 V3V s Analog Equalizer Concept (2) 7

9 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalized output pulses: Rise time = voltage swing/slew rate Rise time nearly constant over different channels! Analog Equalizer Concept (3) V3V3 8

10 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Path V out 9

11 EECS 270C / Winter 2014Prof. M. Green / UC Irvine f (Hz) Equalizer Frequency Response V control 10

12 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Simulations indicate that ISI correlates strongly with FFE transition time t eq. Optimum t eq is observed to be 60 ps. Nonlinearities affect pulse shape, but not location of zero crossings. t eq = 75ps PW = 86ps t eq = 60ps PW = 100ps t (ns) V FFE t eq = 45ps PW = 108ps ISI & Transition Time 11

13 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Slicer Restores full logic levels Exhibits controlled transition time 12

14 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedback Path 13

15 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Transition Time Detector DC characteristic: Rectification & filtering done in a single stage. Transient Characteristic: t (a) (b) (a) (b) I SS C SS VSVS V+V+ V-V- 14

16 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Integrator 15

17 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Detector + Integrator slope detector slope detector From Slicer t slicer = 60ps From FFE t FFE V control + _ t (ns) V control (mV) 60ps 45ps 15ps 75ps 90ps FFE transition Time t FFE 16

18 EECS 270C / Winter 2014Prof. M. Green / UC Irvine + _ KdKd KdKd K eq t slicer t eq detector feedforward equalizer integrator H(s)H(s) V control K eq = 1.5 ps/mV K d = 2.5 mV/ps int = 75ns System Analysis 17

19 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Measurement Setup Die under test 2 31 PRBS signal applied to cable EQ inputs EQ outputs 18

20 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Measured Eye Diagrams 4-foot RU256 cable (-5 dB 5 GHz ) 15-foot RU256 cable (-15 dB 5 GHz) EQ input EQ output 4.0 ps rms jitter 3.9 ps rms jitter 19

21 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Supply voltage3.3 V Power Dissipation350 mW (155 mW not including output driver) Die Size0.81mm X 0.87mm Output Swing490 mV single-ended p-p Random Jitter4.0 ps rms (4-foot cable) 3.9 ps rms (15-foot cable) Summary of Measured Performance Presented at ISSCC Feb

22 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Equalization vs. Compensation Equalization is accomplished by inverting the transfer function of the channel. Compensation is accomplished only by canceling the ISI at each unit interval. Electronic Dispersion Compensation (EDC) refers to the electronics that accomplishes compensation of copper or optical transmission media. EDC is becoming especially critical as bit rates increase on legacy equipment (e.g., backplane, optical connectors, optical fiber). 21

23 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Pre-Cursor/Post-Cursor ISI T Input pulse (no ISI): Output pulse: 0 cursor pre-cursor ISI post-cursor ISI T 0 22

24 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Equalization (FFE) Idea: To cancel ISI, subtract a weighted & delayed version of the pulse: d0d0 d -1 output pulse: output pulse delayed by T: Result with 0 pre-cursor ISI: 23

25 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Equalization (2) T a1a1 Time domain: Frequency domain: + _ 24

26 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Equalization (3) T a1a1 TT a0a0 a2a2 anan N-tap FFE structure: FFE can cancel both pre- and post-cursor distortion. 25

27 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Equalization (4) I SS V0V0 V1V1 V2V2 RR V out + _ 3-tap summing circuit: Coefficients set by g m of each differential pair. negative coefficient 26

28 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Feedforward Equalization (5) Fractional spacing: 1-tap T-spaced FFE frequency response 1-tap T/2-spaced FFE frequency response 5-tap T-spaced FFE eye diagram 5-tap T/2-spaced FFE eye diagram 27

29 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Adaptation (1) Assume original sequence D in (k) is known. Define error signal e(k) as: ^ where D out (k) is an appropriately delayed version of D in (k). ^ Steepest Descent Algorithm: Algorithm moves coefficients in direction of decreasing mean-square error. Step size µ should be made sufficiently small to guarantee convergence. Requires knowledge of properties of mean-square error; usually not available. step size a1a1 a2a2 optimum setting 28

30 EECS 270C / Winter 2014Prof. M. Green / UC Irvine ^ ^ FFE output signal: Adaptation (2) Least mean-square (LMS) algorithm: both signals are available on chip. Analog version of LMS: 29

31 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Adaptation (3) 1. Training Sequence A training sequence with known properties is sent through the channel + equalizer. The equalizer output is compared to the original sequence and an error signal is generated. 2. Blind Adapation Adaptation is continually performed while system is running. Only limited properties of the signal are known. An error signal must somehow be generated without having the original sequence. Types of adaptation: 30

32 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Adaptation (4) FFE ^ + _ Slicer restores logic levels and opens eye vertically. Bit sequences at slicer input & input are identical. Slicer has no effect on placement of zero crossing. Slicer can be realized using CML buffers with sufficient gain and speed. Generation of error signal: 31

33 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Decision Feedback Equalization (DFE) T a1a1 TT a0a0 a2a2 anan FFE structure: Noise applied to FFE input will be retained (perhaps filtered) at the output. DFE structure: TTT b1b1 b2b2 bmbm

34 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Decision Feedback Equalization (2) Slicer is embedded in the structure; D out is a digital signal. Delay elements are digital -- commonly realized by DFFs. Use of slicer suppresses input noise. Cancels post-cursor distortion only. TTT b1b1 b2b2 bmbm

35 EECS 270C / Winter 2014Prof. M. Green / UC Irvine TTT b1b1 b2b2 bmbm Decision Feedback Equalization (3) 2/3 1/ /3 (desired) 1-tap example: post-cursor distortion consistent with Tap weights provide a look-up table, canceling post-cursor distortion based on last m bits of output sequence. DFE can sometimes latch up with wrong tap weights during adaptation. 34

36 EECS 270C / Winter 2014Prof. M. Green / UC Irvine T a1a1 TT a0a0 a2a2 anan TTT b1b1 b2b2 bmbm FFE + DFE Combined FFE and DFE can be used to cancel both pre- and post-cursor distortion with low noise. 35

37 EECS 270C / Winter 2014Prof. M. Green / UC Irvine Front-End Circuits for DSP-Based Receivers from channel Programmable Gain Amplifier (PGA): V in PGAADC AGC VCVC VAVA D out [1:n] where Automatic Gain Control Linear in dB gain characteristic gives settling time independent of input amplitude. ADC requires strict control over its input amplitude V A. 36

38 EECS 270C / Winter 2014Prof. M. Green / UC Irvine PGA Design 1. Differential Pair: VCVC + _ V in+ V in- I out- I out+ I SS For biasing in weak inversion: 2. Source Degeneration: 2R S V in+ V in- I out- I out+ 3. Op-Amp with Feedback: V in + _ V out + _ RSRS RSRS RfRf RfRf R S varied with constant dB per step. 37

39 EECS 270C / Winter 2014Prof. M. Green / UC Irvine PGA Example (1) Realization of R S : 2 dB steps C.-C. Hsu, J.-T. Wu, A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier, JSSC, Oct. 2003, pp

40 EECS 270C / Winter 2014Prof. M. Green / UC Irvine PGA Example (2) gain of single diff. pair where N = number of diff. pairs turned on J. Cao, et al., A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s links over backplane and multimode fiber, ISSC 2009, pp

41 Track & Hold Circuit The T/H circuit is comprised of two switch-capacitor stages and an amplifier which provides gain and isolation. Dummy switches are used to cancel channel charge injection and achieve better linearity. 40

42 Simulation Results T/H differential output for f in = 1.5 GHz and f s =10 GS/sec 41

43 High-speed Comparator High-Level Clocking: Improves isolation between the input and output, reducing kickback from output. Cascoding of the clock switches reduces the Miller effect of the input transistors. Reduced headroom 42

44 Comparator/Latch Results (1) 43

45 Metastable Behavior (1) Metastable event T/H output Comp./Latch output What is the probability of this error occurring? 44

46 Metastable Behavior (2) RR CtCt CtCt v1v1 + v2v2 + t 45

47 Metastable Behavior (3) V in (analog) V out (digital) V dec +V dec 2 2V dec V LSB V dec = minimum detectable logic level = minimum input at t = 0 so that output level is V dec at t = T/2 Error probability: Including comparator gain: 46

48 Metastable Behavior (4) t Recall: For error-free operation after half-clock period: Error probability: 47

49 Additional high-speed latches following the comparator/latch stage reduces probability of metastable events at the output. Latch output Reducing Metastability Errors 48


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