5 RPC discriminator power Molex4 circuits94-V0MolexUL94 V0Molex20-24 gauge wireMax. current 5A.fuseDiscriminator RPC board internally has +5 Analog, +5 Digital, +3V Digitalthrough low drop regulatorsPower connector need +6V analog, +6V digitalThe board draws 0.42A total current (analog+digital)The current thinking is we will combine analog and digital power at the patchpanel connector at RPC half octant edge.
6 Half octant Module edge Power Connector LV supplies wiresChamber endInside thechamber moduleHalf octantModule edgePower Connector~1.5cmPanel Thickness: 1.60mm (.063") max.MolexMolex4.20mm (.165") Pitch Mini-Fit Jr.™ Receptacle5557 series Dual Row4.20mm (.165") Pitch Mini-Fit BMI™ Plug42475 series Dual Row With Panel Mount Ears(16) position(94V-0)– 14(16) position(94V-0)Molex16 gauge wires, 9A max100 cycles mating12(16) connectors for RPC3Molex16 gauge wires, 9A max100 cycles mating
7 FEM crate VME 6U mechanical form factor All modules has fuse ERNI2mm HM standard9(8)A at 200c per contact94V-0VME 6U mechanical form factorAll modules has fuseTDC 0.6A when power up ~1A at full speed4V (3.3V and 1.2 internally)Clock fanout module ~.8AXmit module ~.4A after power up, <1A a full speedL1 trigger output moduledesign in progressClock Master0.9V at 5.5V (one per rack)1.1A at 4V
8 High Voltage Power supply We use CAEN SY1527LC crate supply8 U sizeRPC1N and 1S probably can just share one power supplyhow about station 2, 3Do we need a patch (fanout) panel
9 DC power distributionAfter half octant module, all discriminator board power(2 wires per module) should be wire to rack.16*6 RPC discriminator for station 3DC power fanout at din rail mounted fuse block at the FEM rack (~1A fuse)Do not share power supply between station.Use Low noise converter pack (QPAC)For the FEM crate powerdo not share power between crates.
10 HBD crate power connection (back view) with Bus BarAnalog GND-3.5V+4V-3.5VClock fanout cableMeritec (-048)UL 94V-0Bus Bar5V(4V)Digital GND
12 Channel count etc… (one side) Station1a+b23totalChannel3072384828729792Channel per FEM (TDC)6465FEM (TDC)48190Disc Board96128380L1 trigger Fibers81632FEM/ fibers64Support board/crateFEM/crate12CratesThe crate size is like 6U VME crate.I would like to limit the length discriminator cable to 10 meters.(to be tested about jitters)The RPC2, 3, we will need to find the crate space near the detector.Crate need to be recess in the rack. Cable routing space needed in front of the crate.
13 What half octant station 2,3 need 6 discriminator boards, 3 TDC modules for station 3 half octant, 8 discriminator boards, 4 TDC modules for station 2 half octant.Don’t know we should have one crate or 2 crates for the coming run.Timing issuesSome thing we need to thinks about…We only need one DCM board with maximum 2 FE3 daughter card.One more granule, we also need one GTM.We also need 2 RPC L1 trigger boardThe slow control will done with Ethernet (packet transfer).Backup solution will be slow serial download cableI assume this will become UC/Nevis responsibility
14 Electronics statusWe have received prototype discriminator board a while ago, one assembled.The two assembled TDC modules was received about one week ago.We have received 100 cable adapter board last Friday. We assembled one example.
15 Electronics test done so far Check out discriminator serial download stringsset discriminator threshold DACFire test pulse and see the output LVDS signalCouple directly into the input amplifyTDC moduleVerify serial downloadread data back in offline modeThrough the clock master moduleFire TDC module internal test pulse, compare TDC value vs. test pulse stepsMore detail test works need to be done to characterize the system.
16 internal test pulse vs. TDC value TDC moduleinternal test pulse vs. TDC valuedead regionTDCTDCChannel 17Channel 18One beam crossingInternal test pulse stepInternal test pulse stepTDC internal test pulse is generated with both edge of the 320MHz clock(i.e. 64 steps, ~1.6ns per step)
17 Clockmaster software Clock master module interface use Motorola Coldfire 5282 evaluation board(ethernet) slowdown loadInterface to the GTM to distribute clocks, L1 trigger and test pulseAlex has able to build uCLinux for the 5282 evaluation boardwe will be working together to build the software to control the FEE system.
18 What happen next More testing Built L1 trigger board 4 months? ProblemThere is only one test stand, like to build moreProduction issue on the backplane, crate, clock master module, xmit, clock fanout etcThis will become problem to has test stand in BNL and BoulderWhen will the production start