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S CALING T HE S PEEDUP OF MULTI - CORE CHIPS BASED ON A MDAHL S LAW A.V. Bogdanov, Kyaw Zaya DUBNA, 2012 1.

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Presentation on theme: "S CALING T HE S PEEDUP OF MULTI - CORE CHIPS BASED ON A MDAHL S LAW A.V. Bogdanov, Kyaw Zaya DUBNA, 2012 1."— Presentation transcript:

1 S CALING T HE S PEEDUP OF MULTI - CORE CHIPS BASED ON A MDAHL S LAW A.V. Bogdanov, Kyaw Zaya DUBNA, 2012 1

2 S PEEDUP IN PARALLELISM Architecture of the machines Operation Systems Memory and processor resources Number of processor Problem size The use of algorithms 2

3 Constant problem size scaling Independent on number of processors Using Amdahl's Law as an argument against massively parallel processing is not valid The serial percentage is not practically obtainable 3

4 -. Where, N - number of processors α - The proportion of successive calculations β, γ - parameters characterizing of the network 4

5 T YPES OF MULTI - CORE CHIPS 1.Symmetric multi-core chip 2.Asymmetric multi-core chip 3.Dynamic multi-core chip 5

6 S YMMETRIC MULTI - CORE CHIP Where, ( f)= software fraction that is parallelizable n = the total number of BCE ( base core equivalents) r= number of BCE on a kernel Perf(r)= performance of r number cores Processor Memory I/O 6

7 A SYMMETRIC MULTI - CORE CHIP Common Memory I/O Private memory Processor Private memory 7

8 D YNAMIC MULTI - CORE CHIP Sequential mode Parallel mode 8

9 Advantages of multi-core chips Better throughput : it improves the performance of computer systems by allowing parallel processing of segments of programs. Better reliability: It provides a built –in backup. If one of the CPUs breaks down, the other CPUs automatically takes over the complete workload until repairs are made. Hence, multiprocessor systems have better reliability. Better utilization of resource : In additions to the CPUs, it also facilitates more efficient utilization of all the other devices of the computer system. Disadvantages of multi-core chips A large main memory is required. A very sophisticated operating system is required to schedule, balance and co-ordinate the input, output and processing activities of multiple CPUs. 9

10 S PECIFICATIONS OF T-P LATFORMS C LUSTER T-Platforms Cluster T-EDGE96, HPC – 0011828-001 CPU2x Intel E 5335 (2.0 GHz) CommunicatorInfiniband 20 Gb/s Disk Memory(per node) 160 Gb GPU- RAM(per Node)16 Gb Total Ram Amount786Gb Total48 nodes, 384 cores Peak Efficiency3,07 Tflops 10

11 Figure. Speedup Testing on T-Platforms Cluster 11

12 B ENCHMARKING THE T-P LATFORMS C LUSTER The test result of NPB LU Class C 12

13 C ONCLUSION 13 New Technologies and Architectures Clustering problems Modifications on new types of processor

14 T HANK Y OU 14


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