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Design and Testing of a Radiation Hardened 13-bit 80 MS/s Pipeline ADC Implemented in a 90nm Standard CMOS Process B. Vaz, N. Paulino *, J. Goes *, M.

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Presentation on theme: "Design and Testing of a Radiation Hardened 13-bit 80 MS/s Pipeline ADC Implemented in a 90nm Standard CMOS Process B. Vaz, N. Paulino *, J. Goes *, M."— Presentation transcript:

1 Design and Testing of a Radiation Hardened 13-bit 80 MS/s Pipeline ADC Implemented in a 90nm Standard CMOS Process B. Vaz, N. Paulino *, J. Goes *, M. Rodrigues, P. Faria, R. Monteiro, N. Penetra, T. Domingues Silicon and Software Systems Limited * Also with Universidade Nova de Lisboa

2 Outline Introduction Circuit specifications Architecture Architecture optimization Electrical design Radiation hardening design procedures Experimental results

3 Introduction High speed, high resolution ADCs are very important for communication and imaging systems. In space applications the ADCs need to work in a harsh environment, subjected to severe temperature variations and high energy radiation effects. The objective is to develop and implement in silicon a new high-speed high-resolution ADC that improves linearity, energy-efficiency, cost and reliability for space applications

4 ADC specifications Resolution of 13-bits and effective-number-of-bits (ENOB, e.g. linearity) equivalent to 10.5-bits (un-calibrated mode); Sampling frequency (e.g. conversion speed) of 80MS/s; Energy-efficiency better than 0.7 pico-Joule per conversion step; Standard 90nm 1-poly 8-metals CMOS manufacturing process to lower costs and nominal operating voltage of 1.2V (TSMC 90nm LP); Robustness of the custom designed mixed analogue-digital sections against supply voltage variations, temperature variations and space radiation effects;

5 Block diagram

6 Pipeline ADC Architecture

7 Architecture optimization The ADC architecture was optimized using a proprietary tool in order to achieve the optimum power-efficiency for the target performance specifications. The ADC architecture optimization takes into account the thermal noise, the power dissipation, the differential non-linearity (DNL) and the total ADC capacitance. The best architecture optimization resulted in an ADC with three different pipeline stages and four different amplifiers. The optimizer provides another important set of design outputs including: –optimum values for the unit capacitances required in each stage; –optimum values for the compensation capacitances required in each stage; –biasing currents to be used in the amplifiers; –GBW specification for the amplifiers.

8 Electrical design (1) The selected amplifier topology uses a folded- cascode input stage followed by a differential-pair second-stage. Enhanced cascode-compensation is used instead of the conventional Miller compensation in order to improve the bandwidth. The amplifiers are optimized using a proprietary optimization tool. A key input to the system is a file containing all relevant process technology parameters which are specific to the chosen fabrication technology. The specifications for each amplifier are obtained during the architecture optimization.

9 Electrical design (2) The amplifier optimization takes into account the following key opamp features: –low frequency gain –product gain-bandwidth –output swing –slew-rate –settling time –excess noise factor, –gate area. Furthermore, the optimization is performed considering 17 different design corners simultaneously The complete ADC is simulated in all the relevant corners in order to verify the design

10 Radiation effects in CMOS technology (1) An ionizing particle or photon striking a CMOS circuit results in the creation of electron-holes pairs. If the event occurs in doped silicon the resulting charge will dissipate in a short time because of the low resistivity of the material. If the energy of the ionization particle is very high, it can cause the creation of a large amount of carriers within the integrated circuit structure. This can result in an instantaneous large current known as Single Event Effect (SEE), which can be further divided into SEU (single event upset) and SEL (single event latch-up).

11 Radiation effects in CMOS technology (2) When an electron-hole pair is created in the oxide, the electron will disappear faster than the hole because the mobility of the electron is much higher than the mobility of the hole. The holes will tend to accumulate over time close to the interface layer between the oxide and Silicon, resulting in a positive charge that builds up over time. This is know as the total ionization dose effect (TID).

12 Radiation effects in CMOS technology (3) TID Effects in the CMOS technology: –The charge accumulation in the gate of a NMOS transistor causes its Vt voltage to decrease. –The charge accumulation in the gate of a PMOS transistor causes the Vt voltage of the PMOS transistor to increase –The charge build-up in the bird's beak regions around the NMOS transistors causes two parasitic N channels to appear and a current can flow between the drain and source of the transistor. –The charge build-up in the field oxide region can create an N channel in the P substrate under the oxide and current can now flow between two previously unconnected circuit nodes.

13 Radiation hardening design procedures (1) At an architecture level, the pipeline ADC architecture is naturally robust to offset variations in the comparators because it uses digital correction. Whenever possible the electrical design will use low V Dsat values in the transistors in order to have an extra voltage margin to accommodate for Vt variations. The comparators are designed to have a low offset voltage, also to accommodate the Vt variations. The circuits are biased using current mirrors which compensates for the variation of the Vt voltages. The parasitic N channels that occur under the field oxide can be interrupted using P+ guard rings connected to ground.

14 Radiation hardening design procedures (2) The guard rings also improve the robustness of the circuit to SEE, because they provide a path for the carriers that are created by high energy particles, to dissipate quickly and increase the resistance in the parasitic NPNP structure making it harder for a latch up to occur. Some key transistors use enclosed layout in order to eliminate the parasitic N channels that appear on the edges of the NMOS transistors (birds beak region). The foundry waved the DRC error caused by this transistor layout. However, there is no electrical model for this type of transistor.

15 Enclosed layout transistor

16 Chip Layout ADC core area is only 0.66mm 2

17 Experimental results (1) The radiation test of the ADC was performed by TRAD The measurement of TID effects in the performance parameters of the ADC (TID total dose of 100 krad(Si) was realized using 5 samples plus one reference. –The test board and package used in these tests introduced a performance degradation in the measured ADC parameters. –The ADC was evaluated at a sampling frequency of 40 MHz. Three samples were irradiated with heavy ions with energies from 1 to 70MeV.cm².mg-1 to verify for SEL events.

18 Experimental results (2) In order to measure the performance of the ADC a dedicated 4 layer PCB with the ADC die on the board connected using direct bonding (Chip-On-Board technology) was used. The measured results using this board are the following (ADC operating in un-calibrated mode): VDD (V)SFDR (dB)THD (dB)SNR (dB)SINAD (dB)ENOB (bit)

19 Reference voltage TID test results

20 DNL TID test results

21 SNR TID test results

22 THD TID test results

23 ENOB TID test results

24 SEL test results No SEL observed during this test under a Xenon irradiation (LET = MeV.cm²/mg) with a total fluence equal to 1E+7 #/cm².

25 Conclusions The circuit is robust against SEL events. The TID test results indicate that the ADC performance is not affected by the radiation. However the PCB board used in the TID test introduced a significant performance degradation (about 2 bits in the ADC ENOB). This degradation could mask some minor radiation effects in the ADC performance.


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