Presentation on theme: "VLSI DESIGN 1998 TUTORIAL Part 1. Core Building Blocks and Building Systems using Cores Rajesh K. Gupta University of California, Irvine. What are cores?"— Presentation transcript:
VLSI DESIGN 1998 TUTORIAL Part 1. Core Building Blocks and Building Systems using Cores Rajesh K. Gupta University of California, Irvine. What are cores? What are cores? Building systems using cores Challenges in using cores
Advanced RISC Machines (ARM ) A family of 32-bit RISC processor cores ARM6, ARM7: MPU with Cache, MMU, Write Buffer and JTAG ARM7TDMI :ARM7 with Thumb ISA, ICE, Debug & MPY ARM8 : cached, low power, 5-stage pipe (vs 3 in others) StrongARM1, StrongARM2: available as Digital SA-110 (21285) Piccolo: DSP co-processor for ARM, shares system bus (AMBA) –support for Viterbi, bit manipulation operations –four nestable zero-overhead hardware loop constructs –splittable ALU, 1 cycle dual 16-bit operations –saturation arithmetic –1024 point in place complex radix 2 FFT in 33,331 cycles Manufacturing partnerships and/or licensing with –Cirrus logic, GEC Plessey, Sharp, TI and VLSI Tech.
1110 001 10 01001 Rd 0 Rd Constant 0000 Constant 16-bit Thumb instr. 32-bit ARM instr. always maj. opc.min. opc.dest. and src.zero extended ADD Rd #constant ARM Enhancements: Thumb ISA 8- or 16-bit external, 32-bit internal Thumb instruction set is a subset of 32-bit ARM instruction set –16-bit instructions –expanded into 32-bit ARM instructions at run time without any penalty Up to 65-70% smaller code size compared to ARM 130% of ARM performance with 8/16 bit memory 85% of ARM performance with 32-bit memory