Presentation on theme: "Fault Coverage Analysis of RAM Test Algorithms"— Presentation transcript:
1Fault Coverage Analysis of RAM Test Algorithms Marc RiedelMcGill University, Montreal, CanadaJanusz RajskiMentor Graphics, Wilsonville, Oregon
2Outline Motivation Fault Models Methodology and Complexity Fault Simulation ResultsConclusions
3Motivation Functional Memory Testing Coverage Measures Needed A multitude of fault models and test schemes proposed.Quality of fault coverage difficult to assess.Coverage Measures NeededTo evaluate and rank existing test algorithms:Deterministic/regular tests.Pseudo-random/irregular tests.To validate new test schemes for:Embedded memories and BIST designs.Specialized memory architectures (e.g., multiport, FIFO).
4Functional Cell Array Model Bit-addressable 2-D array of binary storage elements:.......Operations: read, write-0, write-1.
5Functional Fault Behavior Sensitized/desensitized by write operations.Detected by read operations.writeUnsensitizedSensitizedreadDetected1 / 00 / 1write
6Cell Array Fault Models Single Cellstuck-at, transition, stuck-open, data-retentionidempotent, inversion, state, dynamic(2-cell and 3-cell versions)CouplingAND-type, OR-type(2-cell and 3-cell versions)Bridgingactive, passive, static(type I and type II neighborhoods)NeighborhoodPattern Sensitive
7Fault Model Specification Fault models are specified as inputs, not hard-coded.ExampleFormat1sensitization< write op. >< mem. pattern >< write op. >.< mem. pattern >.desensitization< write op. >< mem. pattern >< write op. >.< mem. pattern >.sensitized faultmem. patternwrite op.1
8Ex.: 2-cell OR-type Bridging Fault Operationabsensitizationwrite-1, awrite-1, babwrite-0, a11write-0, b11read to either cell returns OR(a,b)desensitizationwrite-0, a1write-0, b1write-1, a1write-1, b1
9Coverage AnalysisSimulation performed for arbitrary test sequences.write-1,< add. >case: writeread,< add. >Determine which faults are sensitized or desensitized.write-0,< add. >write-1,< add. >case: readread,< add. >..Classify all sensitized faults as covered..
10Sensitization & Desensitization A write operation can sensitize/desensitize several faults.Examplefaults in cells y , y , y , y sensitized by write operation1234active NPSFxp214y123433transition in nbh. patternp , p , p , p sensitizes fault1234
11Delayed State Transitions Sensitization/desensitization occur after a time delaytD.Used to model retention faults, e.g., "sleeping-sickness" failures in DRAMS:1tD1
12Multiple Faults Error masking Multiple sensitizations xyzCFid(y and zCFid(x and z1Error maskingCFid(y and zCFid(x and yxyz1Multiple sensitizations
13Multiple Faults (cont.) Sensitized faults change the memory pattern.This affects the sequence of sensitization/desensitization of other faults.Exampleno faults sensitizedfault A sensitizedfault B sensitizedfaults A and B sensitized1ABC11111111111111ACACAC11111111BBBthe pattern surrounding cell C is all 1’sa sleeping-sickness fault is sensitized
14Complexity NPSFs k-cell coupling faults with respect to the test sequence length tNPSFswith respect to the neighborhood size kk-cell coupling faultswith respect to the memory size n & number of coupled cells kNPSFs: cells in physical proximity.Coupling faults: cells located anywhere in memory array.
15Examples of Test Algorithms March XMarch C-1GALPAT
16Simulation Results for March X ABFSCFlocal 3-cellFault ClassFC (%)25.050.0CFidglobal 2-cell75.0100StaticPassiveType II NPSFFault ClassFC (%)0.391.76ActiveType I NPSF6.2515.6256-bit memory (16 rows x 16 columns)
17Simulation Results for March C- ABFSCFlocal 3-cellFault ClassFC (%)50.0100CFidglobal 2-cellStaticPassiveType II NPSFFault ClassFC (%)0.783.52ActiveType I NPSF12.531.2256-bit memory (16 rows x 16 columns)
18Simulation Results for GALPAT ABFSCFlocal 3-cellFault ClassFC (%)48.279.9100CFidglobal 2-cell99.7StaticPassiveType II NPSFFault ClassFC (%)0.810.984.10ActiveType I NPSF11.715.640.6256-bit memory (16 rows x 16 columns)
20Conclusions General RAM fault simulation methodology. Library of over 25 functional fault models.Coverage statistics for over 40 test algorithms.Application:Evaluation of arithmetic BIST schemes for memories.