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Testing Semiconductor Memories Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University Cheng-Wen Wu.

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Presentation on theme: "Testing Semiconductor Memories Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University Cheng-Wen Wu."— Presentation transcript:

1 Testing Semiconductor Memories Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University Cheng-Wen Wu

2 mbist1.10Cheng-Wen Wu, NTHU 2Outline Introduction RAM functional fault models and test algorithms RAM fault-coverage analysis Cocktail-March for testing word- oriented memories Testing multi-port RAMs Testing CAMs Testing flash memories

3 mbist1.10Cheng-Wen Wu, NTHU 3 Introduction Memory testing is a more and more important issue RAMs are key components for electronic systems Memories represent about 30% of the semiconductor market Embedded memories are dominating the chip yield Memory testing is more and more difficult Growing density, capacity, and speed Emerging new architectures and technologies Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc. Cost drives the need for more efficient test methodologies IFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc. Test automation is required Failure analysis, fault simulation, ATG, and diagnostics BIST/BIRA/BISR generation

4 mbist1.10Cheng-Wen Wu, NTHU 4 Typical RAM Production Flow Wafer Full Probe TestMarking Final Test Shipping QA Sample Test Visual Inspection Burn-In (BI) Post-BI TestLaser RepairPackaging Pre-BI Test

5 mbist1.10Cheng-Wen Wu, NTHU 5 Scope of RAM Testing Parametric Test: DC & AC Reliability Screening Long-cycle testing Burn-in: static & dynamic BI Functional Test Device characterization Failure analysis Fault modeling Simple but effective (accurate & realistic?) Test algorithm generation Small number of test patterns (data backgrounds) High fault coverage Short test time

6 mbist1.10Cheng-Wen Wu, NTHU 6 RAM Models Behavior Level Verilog/VHDL Function Level Verilog/VHDL/Block diagram Normally not synthesizable Circuit Level Spice/Schematic Layout Level GDS-II/Geometry Who should provide the model?

7 mbist1.10Cheng-Wen Wu, NTHU 7 Memory Function Model Example

8 mbist1.10Cheng-Wen Wu, NTHU 8 RAM Fault Models (Static) Address-Decoder Fault (AF) No cell accessed by certain address Multiple cells accessed by certain address Certain cell not accessed by any address Certain cell accessed by multiple addresses Stuck-At Fault (SAF) Cell (line) SA0 or SA1 Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0

9 mbist1.10Cheng-Wen Wu, NTHU 9 RAM Fault Models (Static) Bridging Fault (BF) Short between cells AND type or OR type Stuck-Open Fault (SOF) Cell not accessible due to broken line Neighborhood Pattern Sensitive Fault (NPSF) Active (Dynamic) NPSF Passive NPSF Static NPSF

10 mbist1.10Cheng-Wen Wu, NTHU 10 RAM Fault Models (Static) Coupling Fault (CF) State Coupling Fault (CFst) Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given state Inversion Coupling Fault (CFin) Transition in coupling cell complements (inverts) coupled cell Idempotent Coupling Fault (CFid) Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0

11 mbist1.10Cheng-Wen Wu, NTHU 11 RAM Fault Models (Dynamic) Recovery Fault (RF) Sense Amplifier Recovery Fault (SARF) Sense amp saturation after reading/writing long run of 0 or 1 Write Recovery Fault (WRF) Write followed by reading/writing at different location resulting in reading/writing at same location Write-after-write recovery fault Read-after-write recovery fault Results in functional faults---detected at high speed (e.g., GALROW/GALCOL) Disturb Fault (DF) Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same cell)

12 mbist1.10Cheng-Wen Wu, NTHU 12 RAM Fault Models (Dynamic) Data Retention Fault (DRF) DRAM Refresh Fault Refresh-Line Stuck-At Fault Leakage Fault Sleeping Sickness---loose data in less than specified hold time (typically tens of ms) SRAM Leakage Fault Static Data Losses---defective pull-up Checkerboard pattern triggers max leakage BIST good for sync with refresh mechanism

13 mbist1.10Cheng-Wen Wu, NTHU 13 Test Time Complexity (100MHz)

14 mbist1.10Cheng-Wen Wu, NTHU 14 RAM Test Algorithm A test algorithm (or simply test) is a finite sequence of test elements A test element contains a number of memory operations (access commands) Data pattern (background) specified for the Read operation Address (sequence) specified for the Read and Write operations A march test algorithm is a finite sequence of march elements A march element is specified by an address order and a number of Read/Write operations

15 mbist1.10Cheng-Wen Wu, NTHU 15 Classical Test Algorithms Zero-One Algorithm [Breuer & Friedman 1976] Also known as MSCAN For SAF Solid background (pattern) Complexity is 4N

16 mbist1.10Cheng-Wen Wu, NTHU 16 Classical Test Algorithms Checkerboard Algorithm Zero-one algorithm with checkerboard pattern Complexity is 4N For SAF and DRF

17 mbist1.10Cheng-Wen Wu, NTHU 17 Classical Test Algorithms Galloping Pattern (GALPAT) Complexity is 4N**2---only for characterization All AFs,TFs, CFs, and SAFs are located 1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; For OC = 0 to N-1, OC != BC; { Read BC; Read OC; } Complement BC; } 3. Write background 1; 4. Repeat Step 2;

18 mbist1.10Cheng-Wen Wu, NTHU 18 Classical Test Algorithms Sliding (Galloping) Row/Column/Diagonal Based on GALPAT, but instead of a bit, a complete row, column, or diagonal is shifted Complexity is 4N**1.5

19 mbist1.10Cheng-Wen Wu, NTHU 19 Classical Test Algorithms Butterfly Algorithm Complexity is 5NlogN 1. Write background 0; 2. For BC = 0 to N-1 { Complement BC; dist = 1; While dist <= mdist /* mdist < 0.5 col/row length */ { Read dist north from BC; Read dist east from BC; Read dist south from BC; Read dist west from BC; Read BC; dist *= 2; } Complement BC; } 3. Write background 1; repeat Step 2;

20 mbist1.10Cheng-Wen Wu, NTHU 20 Classical Test Algorithms Moving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976] For functional and AC parametric test Functional (13N): for AF, SAF, TF, and most CF Parametric (12NlogN): for Read access time 2 successive 2 different addresses with different data for all 2-address sequences differing in 1 bit Repeat T2~T5 for each address bit GALPAT---all 2-address sequences

21 mbist1.10Cheng-Wen Wu, NTHU 21 Classical Test Algorithms Surround Disturb Algorithm Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows 1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; } 2. Repeat Step 1 with complementary data;

22 mbist1.10Cheng-Wen Wu, NTHU 22 Classical Test Algorithms Zero-one and checkerboard algorithms do not have sufficient coverage Other algorithms are too time-consuming for large RAM Test time is the key factor of test cost Complexity ranges from N 2 to NlogN Need linear-time test algorithms with small constants March test algorithms

23 mbist1.10Cheng-Wen Wu, NTHU 23 March Tests Zero-One (MSCAN) Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979] OR-type address decoder fault AND-type address decoder fault MATS+ [Abadir & Reghbati 1983] For both OR- & AND-type AFs and SAF

24 mbist1.10Cheng-Wen Wu, NTHU 24 March Tests Marching 1/0 [Breuer & Friedman 1976] For AF, SAF, and TF MATS++ [Goor 1991] Also for AF, SAF, and TF Complete and irredundant

25 mbist1.10Cheng-Wen Wu, NTHU 25 March Tests March X For AF, SAF, TF, & CFin March C [Marinescu 1982] For AF, SAF, TF, & all CFs---redundant March C- [Goor 1991] Also for AF, SAF, TF, & all CFs---irredundant

26 mbist1.10Cheng-Wen Wu, NTHU 26 March Tests Limitations Sequential faults in address decoders RF NPSF (9N-2) for 2-CF [Marinescu 1982] (2NlogN+11N) for 3-CF [Cockburn 1994] Solutions Address sequence variation Hopping Pseudorandom

27 mbist1.10Cheng-Wen Wu, NTHU 27 Coverage of March Tests Extended March C- (11N) has a 100% coverage of SOF

28 mbist1.10Cheng-Wen Wu, NTHU 28 Testing Word-Oriented RAM Background bit is replaced by background word MATS++: Conventional method is to use logm+1 different backgrounds for m-bit words m=8: , , , and Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N

29 mbist1.10Cheng-Wen Wu, NTHU 29 Cocktail-March Algorithms Motivation: Repeating the same algorithm for all logm+1 backgrounds has redundancy Different algorithm targets different faults Approach: Use multiple backgrounds in a single algorithm run Merge and forge different algorithms and backgrounds into a single algorithm Good for word-oriented memories

30 mbist1.10Cheng-Wen Wu, NTHU 30 March-CW Algorithm: March C- for solid background (0000) Then a 5N March for each of other standard backgrounds (0101, 0011): Result: Complexity is (10+5logW)N, where W is word length and N is word count Test time is reduced by 39% if W=4, as compared with extended March C- Improvement increases as W increases

31 mbist1.10Cheng-Wen Wu, NTHU 31 Comparison (Full Coverage)

32 mbist1.10Cheng-Wen Wu, NTHU 32 Testing NPSF NPSF test approaches Tiling Multi-background march Easy BIST implementation 5-cell neighborhood

33 mbist1.10Cheng-Wen Wu, NTHU 33 NPSF Models Static NPSF (SNPSF) BC forced to a certain state due to a certain deleted neighborhood (DN) pattern Passive NPSF (PNPSF) BC frozen due to a certain DN pattern Active NPSF (ANPSF) BC content changes due to a change in DN pattern Change: a transition in one DN cell, with other DN cells & BC containing a certain pattern Assumptions: Single NPSF Address scramble table is available Memory is bit-oriented Word-oriented memory is tested as multiple bit-oriented ones

34 mbist1.10Cheng-Wen Wu, NTHU 34 Test Strategy Multi-Background March To generate all neighborhood patterns Solid BG (FC < 30%) Another BG

35 mbist1.10Cheng-Wen Wu, NTHU 35 Testing PNPSF March 17N:

36 mbist1.10Cheng-Wen Wu, NTHU 36 Data Background Generation Data backgrounds BG1: all zero BG2: Ar[0], LSB of row address BG3: Ar[1], second bit of row address BG4: Ar[0] Ar[1]

37 mbist1.10Cheng-Wen Wu, NTHU 37 Testing ANPSF March 12N:

38 mbist1.10Cheng-Wen Wu, NTHU 38 Time Complexity 12 N/BG X 8 BG = 96N Detects all NPSFs

39 mbist1.10Cheng-Wen Wu, NTHU 39 Multi-Port Memories Popular architectures k-port (k > 1) n-read-1-write FIFO

40 mbist1.10Cheng-Wen Wu, NTHU 40 2-Port Topology

41 mbist1.10Cheng-Wen Wu, NTHU 41 Inter-Port Word-Line Short * Functional test complexity: O(N 3 )

42 mbist1.10Cheng-Wen Wu, NTHU 42 Inter-Port Bit-Line Short * Functional test complexity: O(N 2 )

43 mbist1.10Cheng-Wen Wu, NTHU 43 Address Scrambling

44 mbist1.10Cheng-Wen Wu, NTHU 44 Reading Neighboring Cells Read neighboring cells to detect inter-port faults: r N, r S, r E, and r W 0/1

45 mbist1.10Cheng-Wen Wu, NTHU 45 TAGS-PS

46 mbist1.10Cheng-Wen Wu, NTHU 46 Dual-Port RAM Test

47 mbist1.10Cheng-Wen Wu, NTHU 47 Compacted Dual-Port RAM Test * Time complexity: 10N

48 mbist1.10Cheng-Wen Wu, NTHU 48 Four-Port RAM Test * Time complexity: 17N

49 mbist1.10Cheng-Wen Wu, NTHU 49 Testing 6-Read-1-Write RAM * Time complexity: 13N

50 mbist1.10Cheng-Wen Wu, NTHU 50 Flash Memory Testing Testing nonvolatile memories: Masked ROM---exhaustive; pseudorandom PROM (OTP) & EPROM---dummy row EEPROM & flash memory---dummy row? Testing flash memory core is hard Customized core and I/O Isolation (accessibility) Reliability issues: disturbances, over program/erase, under program/erase, data retention, cell endurance, etc. Long program/erase time

51 mbist1.10Cheng-Wen Wu, NTHU 51 Flash Memory Overview Flash memory can be programmed and erased electrically Has the advantages of EPROM and EEPROM A stacked gate transistor with both the control gate (CG) and floating gate (FG): G D S P-Si n+n+ n+n+ SourceDrain Control gate Floating gate

52 mbist1.10Cheng-Wen Wu, NTHU 52 Flash Memory Program & Erase ProgramErase Program(1 to 0): channel hot-electron (CHE) injection or Fowler- Nordheim (FN) electron tunneling Erase (0 to 1): FN electron tunneling By the entire chip or large blocks (flash erasure) Different products have different program/erase mechanisms

53 mbist1.10Cheng-Wen Wu, NTHU 53 Flash Memory Cell Types Stacked-gate Split-gate Select-gate Operations: Read, Program, Erase (Flash Erase) As opposed to Read and Write in RAM

54 mbist1.10Cheng-Wen Wu, NTHU 54 Programming Scheme Comparison

55 mbist1.10Cheng-Wen Wu, NTHU 55 NOR-Array Structure

56 mbist1.10Cheng-Wen Wu, NTHU 56 NAND-Array Structure Select (drain) Select (source) WL 1 WL 2 WL 3 WL 4 WL 16 BL i

57 mbist1.10Cheng-Wen Wu, NTHU 57 Disturbance Example (I) NOR-Type Common Ground – Standard (Stacked Gate)

58 mbist1.10Cheng-Wen Wu, NTHU 58 Disturbance Example (II)

59 mbist1.10Cheng-Wen Wu, NTHU 59 Disturbance Example (III)

60 mbist1.10Cheng-Wen Wu, NTHU 60 Disturbance Example (IV)

61 mbist1.10Cheng-Wen Wu, NTHU 61 Gate Program Disturb Fault (GPDF) V(H) V(L) V(Gd) Conditions: 1.Victim cell initial value is a logic 1 2.Aggressor 1 0 (program) Victim 1 0 (program) Control Gate Floating Gate SourceDrain Substrate G SD B

62 mbist1.10Cheng-Wen Wu, NTHU 62 Gate Erase Disturb Fault (GEDF) V(H) V(L) V(Gd) Conditions: 1.Victim cell initial value is a logic 0 2.Aggressor 1 0 (program) Victim 0 1 (erase) Control Gate Floating Gate SourceDrain Substrate G SD B

63 mbist1.10Cheng-Wen Wu, NTHU 63 Drain Program Disturb Fault (DPDF) V(H) V(L) V(Gd) During programming, erased cells on unselected rows on a bit-line that is being programmed may have a fairly deep depletion region formed under them Electrons entering this depletion region can be accelerated by the electric field and injected over the oxide potential barrier to adjacent floating gates Conditions: 1.Victim cell initial value is a logic 1 2.Aggressor 1 0 (program) Victim 1 0 (program)

64 mbist1.10Cheng-Wen Wu, NTHU 64 Drain Erase Disturb Fault (DEDF) V(H) V(L) V(Gd) Conditions: 1.Victim cell initial value is a logic 0 2.Aggressor 1 0 (program) Victim 0 1 (erase) Control Gate Floating Gate SourceDrain Substrate G SD B

65 mbist1.10Cheng-Wen Wu, NTHU 65 Read Disturb Fault (RDF) Control Gate Floating Gate SourceDrain Substrate G SD B Conditions: 1. Occurs on the selected cell 2. Cell initial value is logic 1 Soft-Program During the read operation, hot carriers can be injected from the channel into the FG even if at low gate voltages

66 mbist1.10Cheng-Wen Wu, NTHU 66 Over Erase Fault (OEF) Flash memory erase mechanism is not self-limiting Threshold voltage can be low enough to turn the cell into a depletion-mode transistor Fault behavior: An unselected cell in the same bit-line has excessive source-drain leakage current Reading that cell leads to incorrect value (like DEDF) Cannot be programmed correctly (like TF)

67 mbist1.10Cheng-Wen Wu, NTHU 67 Basic RAM Faults for Flash Memory Address-Decoder Fault (AF) Stuck-At Fault (SAF) Transition Fault (TF) Stuck-Open Fault (SOF) Bridging Fault (BF) Coupling faults need not be considered! Replaced by disturb faults

68 mbist1.10Cheng-Wen Wu, NTHU 68 Reliability Consideration Reliability characteristics of floating-gate ICs depend on Circuit density, circuit design, and process integrity Memory array type and cell structure Reliability stressing and testing must then be oriented toward determining the relevant failure rates for the particular array under consideration

69 mbist1.10Cheng-Wen Wu, NTHU 69 Data Retention Fault Retention time: the time from data storage to the time at which a verifiable error is detected from any cause Intrinsic retention times exceed millions of years in the operating temperature range Months at 300°C 1 million years at 150 °C 120 million years at 55 °C Data Retention Fault (DRF) Static leakage Built-in data retention test circuit

70 mbist1.10Cheng-Wen Wu, NTHU 70 Cell Endurance Fault Endurance: a measure of the ability to meet data- sheet specifications as a function of accumulated program/erase cycles Endurance limit is a result of damage to the dielectric around the floating gate caused by electric stresses In many flash devices, the end of endurance is generally caused by hot electron trapping in the charge transport oxide Cell Endurance Fault (CEF) Threshold window shift due to increased program/erase cycles Built-in stress test circuit

71 mbist1.10Cheng-Wen Wu, NTHU 71 Composite Failure Rate Determination 125°C dynamic life stress The 125°C dynamic life stress is the standard MOS memory continuous dynamic read in a burn-in chamber Endurance test The endurance test is the repeated data complementing of floating-gate devices, possibly at temperature extremes Extended data retention stress This test is constituted by a high-temperature bake with a charge polarity that is opposite to the equilibrium state on the floating gate

72 mbist1.10Cheng-Wen Wu, NTHU 72 Typical Test Modes (Characterization) Stress (row/column) Reverse tunneling stress Punch through stress Tox stress DC stress Mass program Weak erase Leak (thin-oxide, bit-line, etc.) Cell current; cell Vt Margin Etc.

73 mbist1.10Cheng-Wen Wu, NTHU 73 Test Patterns A RAM test pattern definition includes both the data pattern and the address pattern The time to read a pattern is the same as the time to write a pattern For flash memories, however, the address and data pattern definitions must be segregated It has long write times relative to the read times Typical data patterns: Solid, checkerboard, random, etc. Typical address patterns: Address increment/decrement, address complement, column/diagonal galloping, etc.

74 mbist1.10Cheng-Wen Wu, NTHU 74 Testing GPDF Flash Program the first column Read all cells except the first column Flash Program any column except the first Read the first column *Assume reading and programming are done column-wise Source: Saluja, et al., Int. Conf. VLSI Design, 2000

75 mbist1.10Cheng-Wen Wu, NTHU 75 Testing GEDF Flash Program all cells Read all cells except the last column Program any column except the last Read the last column *Assume reading and programming are done column-wise Source: Saluja, et al., Int. Conf. VLSI Design, 2000

76 mbist1.10Cheng-Wen Wu, NTHU 76 Test Coverage: Previous Results FaultDCPDCEDDEFGF SAF50% 100% TF12.5%50% 87.5%62.5% AF40%0% 44.5%40% SOF0% 12.5%6.2% CFst25% 50% GPDF33.3%0% 100%33.3% GEDF0%100%75%100% DEDF0%75%100% DPDF0% Source: Saluja, et al., Int. Conf. VLSI Design, 2000

77 mbist1.10Cheng-Wen Wu, NTHU 77 March-Based Flash Test: March-FT {(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)} This Flash memory is NOR type (Stacked gate). Memory size (N) : Test length : 2(chip erase time) (word program time) (word read time) Test time : sec SAF : 100%( / )P.S. TF : 100%( / ) Flash Type = NOR SOF : 100%(65536 / 65536) Gate Type = Stack AF : 100%( / ) Row Number = 256 CFst : 100%( / ) Col Number = 256 GPD : 100%( / ) Word Length = 1 GED : 100%( / ) Chip erase time = 3 sec DPD : 100%( / ) Word program time = 9u sec DED : 100%( / ) Word read time = 70n sec RD : 100%(65536 / 65536) OE : 100%(65536 / 65536)

78 mbist1.10Cheng-Wen Wu, NTHU 78 Test Length (Bit-Oriented) Notation: F : Flash time P : Program time R : Read time r : row number c : column number DCP2(F) + 2r(P) + rc(R) DCE(F) + (c+1)r(P) + rc(R) DD(F) + (r+1)c(P) + rc(R) EF2(F) + (rc+2r+c-2)(P) + (2rc+r+c-3)(R) GF2(F) + (rc+2r+c-1)(P) + (2rc+c+r-2)(R) FT2(F) + 2rc(P) + 6rc(R)

79 mbist1.10Cheng-Wen Wu, NTHU 79 Test Length (Word-Oriented) Word length = w: 2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)] Solid: 0000 (1111) Standard: 0101 (1010), 0011 (1100) Ex: word length w = 4 6(F) + 4rc(P) + 8rc(R) solid background testing time standard background testing time

80 mbist1.10Cheng-Wen Wu, NTHU 80 Test Algorithm Generation by Simulation (TAGS) T(N)Test algorithms 2N 3N 4N 5N 6N 7N 8N 9N 10N (f); (r1) (f); (w0); (r0) (f); (r1,w0); (r0) (f); (r1,w0,r0); (r0) (f); (r1,w0,r0); (r0,w0) (f); (r0); (r1,w0,r0); (r0,w0) (f); (r1,w0); (f); (r1,w0,r0); (r0) (f); (r1,w0); (r0); (f); (r1,w0,r0); (r0) (f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)

81 mbist1.10Cheng-Wen Wu, NTHU 81 Embedded Memory Testing Memories are one of the most universal cores In Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area; in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar, ITC-99] In average SOC, memory cores will represent more than 90% of the chip area by 2010 [ITRS 2000] Embedded memory testing is increasingly difficult High bandwidth (speed and I/O data width) Heterogeneity and plurality Isolation (accessibility) AC test, diagnostics, and repair BIST is considered the best solution

82 mbist1.10Cheng-Wen Wu, NTHU 82 Embedded RAM Test Support

83 mbist1.10Cheng-Wen Wu, NTHU 83 RAM BIST Approaches Methodology Processor-based BIST Programmable Hardwired BIST Fast Compact Interface Serial (scan, ) Parallel (embedded controller; hierarchical) Patterns (address sequence) March Pseudorandom

84 mbist1.10Cheng-Wen Wu, NTHU 84 Typical RAM BIST Architecture RAM Test Collar (MUX) BIST Module Controller Comparator Pattern Generator Go/No-Go RAM Controller

85 mbist1.10Cheng-Wen Wu, NTHU 85 Serial March (SMarch) From March C- Serial interface One BIST for all (cascaded) One-bit read/write at a time, but one pattern per cycle Slow No diagnostics Source: Nadeau-Dostie et al., IEEE D&T, Apr Memory Cell Array X Decoder Y Decoder Transparent Serial Data-MUX Addr SISO DQ c c

86 mbist1.10Cheng-Wen Wu, NTHU 86 Syntest MBIST Algorithms: March C- MOVI March C++ Checkerboard Shared controller for multiple RAMs Synthesizable RTL code FSM Data Generator Analyzer ADR Control CE OE WEB A D Q Pass BistFail Finish Source: Syntest

87 mbist1.10Cheng-Wen Wu, NTHU 87 NTHU/GUC EDO DRAM BIST

88 mbist1.10Cheng-Wen Wu, NTHU 88 DRAM Page-Mode Read-Write Cycle

89 mbist1.10Cheng-Wen Wu, NTHU 89 Programmable Memory BIST (PMBIST)

90 mbist1.10Cheng-Wen Wu, NTHU 90 PMBIST Architecture

91 mbist1.10Cheng-Wen Wu, NTHU 91 Controller and Sequencer Controller Microprogram Hardwired Shared CPU core IEEE TAP Sequencer (Pattern Generator) Counter LFSR LUT

92 mbist1.10Cheng-Wen Wu, NTHU 92 Controller

93 mbist1.10Cheng-Wen Wu, NTHU 93 Sequencer

94 mbist1.10Cheng-Wen Wu, NTHU 94 PMBIST Test Modes Scan-Test Mode RAM-BIST Mode Functional faults Timing faults (setup/hold times, rise/fall times, etc.) Data retention faults RAM-Diagnosis Mode RAM-BI Mode

95 mbist1.10Cheng-Wen Wu, NTHU 95 PMBIST Controller Commands

96 mbist1.10Cheng-Wen Wu, NTHU 96 PMBIST Control Sequence

97 mbist1.10Cheng-Wen Wu, NTHU 97 BIST Area Overhead 3% 0.3% Overhead Mem size

98 mbist1.10Cheng-Wen Wu, NTHU 98 Processor-Based RAM BIST Processor

99 mbist1.10Cheng-Wen Wu, NTHU 99 On-Chip Processor-Based RAM BIST BIST program is stored in boot ROM during design phase, and memory BIST is done by executing BIST program Address bus Embedded memory CPU core BOOT ROM DATAI bus DATAO bus Control bus I/O port

100 mbist1.10Cheng-Wen Wu, NTHU 100 Testing RAM Core by On-Chip CPU 6502 assembly program that performs March C- test algorithm.org0HFF00 LDX#$$00 LDA#$$55 M0:STA0000,X INX CPX#$$FF BNEM0 LDX#$$00 M1:LDA0000,X CMP#$$55 BNEERROR LDA#$$AA STA0000,X INX CPX#$$FF BNEM1 LDX#$$ (W0) (R0W1) (R1W0) (R0W1) (R1W0) (R0) March C- algorithm data background write data background to memory read from memory write data background to memory

101 mbist1.10Cheng-Wen Wu, NTHU 101 Test Speed Consideration Processor-BIST speed is lower than dedicated BIST circuit Total clock cycles to implement MARCH C- is O(114N) Table instruction cycles

102 mbist1.10Cheng-Wen Wu, NTHU 102 NTHU Processor-Programmable BIST

103 mbist1.10Cheng-Wen Wu, NTHU 103 Advantages and Disadvantages Advantages Reuse of on-chip CPU core Might need modification Core March elements can be implemented in hardware, allowing different March algorithms to be executed via assembly programming Disadvantages Some address space will be occupied by PPBIST Area overhead

104 mbist1.10Cheng-Wen Wu, NTHU 104 PPBIST Implementation

105 mbist1.10Cheng-Wen Wu, NTHU 105 PPBIST Data Registers

106 mbist1.10Cheng-Wen Wu, NTHU 106 PPBIST Test Procedure CPU write data back ground CPU write start/stop address CPU write MARCH element instruction CPU write START instruction to wrapper BIST core (R0W1) BIST core (R1W0) BIST core (R0W1) BIST core (R1W0) BIST core (W0) BIST core (R0) compare error? complete? write error flag write faulty address write faulty data write complete flag yes no CPU take over

107 mbist1.10Cheng-Wen Wu, NTHU 107 PPBIST Example Using assembly program that performs March C- test algorithm under the proposed BIST scheme START:LDA#$$55 STA 0HFFE0 LDA#$$00 STA 0HFFE1 LDA#$$00 STA 0HFFE2 LDA#$$FF STA 0HFFE3 LDA#$$0F STA0HFFE4 M0:LDA#$$00 STA 0HFFE5 JSRBIST M1:LDA#$$01... END:LDA#$$04 STA 0HFFE6 JMPFINISH BIST:LDA#$$00 STA 0HFFE6 LOOP:LDA0HFFE7 CMP#$$01 BEQ ERROR CMP#$$FF BNE LOOP RTS ERROR:LDA#$$03 STA 0HFFEA JMPFINISH

108 mbist1.10Cheng-Wen Wu, NTHU 108 PPBIST Example Addresses of the registers in the BIST experiment March elements and the corresponding R ME

109 mbist1.10Cheng-Wen Wu, NTHU 109 Experimental Results Total test time in terms of clock cycles The sum of all the March elements' test time plus 30 clock cycles 10N clock cycles to perform March C- Test time of each March element :

110 mbist1.10Cheng-Wen Wu, NTHU 110 Comparison of BIST Methodologies

111 mbist1.10Cheng-Wen Wu, NTHU 111 RAM BIST Compiler Use of RAM cores is increasing. SRAM, DRAM, flash RAM Multiple cores RAM BIST compiler is the trend. BRAINS (BIST for RAM in Seconds) Proposed BIST Architecture Memory Modeling Command Sequence Generation Configuration of the Proposed BIST

112 mbist1.10Cheng-Wen Wu, NTHU 112 BRAINS Outputs Synthesizable BIST design At-speed testing Programmable March algorithms Optional diagnosis support BISD Activation sequence Test bench Synthesis script

113 mbist1.10Cheng-Wen Wu, NTHU 113 BIST Synthesis Flow GUI RAM/BIST Description Parser Compile Engine Memory Library BIST Template Synthesis Cell Library RTL Netlist

114 mbist1.10Cheng-Wen Wu, NTHU 114 NTHU/GUC PMBIST Architecture

115 mbist1.10Cheng-Wen Wu, NTHU 115 PMBIST with Scan Source: Cheng, et al., DFT00

116 mbist1.10Cheng-Wen Wu, NTHU 116 Sequencer Control Module Control Module Address Generator Sequence Generator Command Generator Error Handling Module address command error info. go error signature

117 mbist1.10Cheng-Wen Wu, NTHU 117 State Diagram of Control Module BIST apply BIST apply BIST done BIST done BIST idle BIST idle BIST apply BIST apply BIST done BIST done BIST idle BIST idle BIST active BIST active For DRAMFor SRAM

118 mbist1.10Cheng-Wen Wu, NTHU 118 DRAM Page-Mode Operation

119 mbist1.10Cheng-Wen Wu, NTHU 119 Memory Specification Techniques Memory Specifications I/O Specification Command Specification Task Specification Delay Constraint Specification AC Parameter Specification Support customized memories.

120 mbist1.10Cheng-Wen Wu, NTHU 120 I/O Specification Four parameters IO_type IO_width IO_latency IO_packet_length IO_type: input, output, or inout IO_width: port width (#bits), can be a constant or specified by user

121 mbist1.10Cheng-Wen Wu, NTHU 121 I/O Specification IO_latency: port latency

122 mbist1.10Cheng-Wen Wu, NTHU 122 I/O Modeling IO_packet_length: #bits packed within a clock cycle for the port

123 mbist1.10Cheng-Wen Wu, NTHU 123 Command Specification Specifies the memorys instructions

124 mbist1.10Cheng-Wen Wu, NTHU 124 Task Specification Specifies a complete memory operation A task can be a single command or a sequence of commands.

125 mbist1.10Cheng-Wen Wu, NTHU 125 Delay Constraint Specification Specifies the minimal time interval between any two tasks

126 mbist1.10Cheng-Wen Wu, NTHU 126 AC Parameter Specification Specifies input and output delays Specified parameters will be inserted into the synthesis script.

127 mbist1.10Cheng-Wen Wu, NTHU 127 Memory Specification Example For ZBT SRAM: Method D = write = {write}; Method D = write = {pre_write, post_write}; The BIST circuit from method A is faster than the one from method B, but it has higher area overhead

128 mbist1.10Cheng-Wen Wu, NTHU 128 Sequence Generation For each March element, the compiler generates the command sequence according to the read task, write task, and minimum delay between the two tasks For example: task read = {A} task write = {B, C} minimum delay between read and write = 10ns clock period = 10 ns Then the (rw) element becomes {A, nop, B, C} One can also optimize the command sequence

129 mbist1.10Cheng-Wen Wu, NTHU 129 Fast Access Mode

130 mbist1.10Cheng-Wen Wu, NTHU 130 Diagnosis Support The BIST circuit scans out the error information (element, address, signature, and polarity) during the diagnosis mode. Assume address 20h stuck-at 64h:

131 mbist1.10Cheng-Wen Wu, NTHU 131 Multiple RAM Cores Controller and sequencer can be shared. controller Test pattern generator Test pattern generator sequencer Ram Core A Ram Core B Ram Core C Test pattern generator sequencer

132 mbist1.10Cheng-Wen Wu, NTHU 132 Experimental Results The Built-In Memory List DRAM EDO DRAM SDRAM DDR SDRAM SRAM Single-Port Synchronous SRAM Single-Port Asynchronous SRAM Two-Port Synchronous Register File Dual-Port Synchronous SRAM Micron ZBT SRAM BRAINS can support new memory architecture easily

133 mbist1.10Cheng-Wen Wu, NTHU 133 Experimental Results

134 mbist1.10Cheng-Wen Wu, NTHU 134 Experimental Results Four single-port SRAM BIST circuits share the same controller and sequencer. Size of the SRAM core: 8K x 16 Original BIST area for single-port SRAM: 1438 (gates) Total area = 1438 * 4 = 5752 (gates) Shared gate count: 3350

135 mbist1.10Cheng-Wen Wu, NTHU 135 Experimental Results 8K x 16 single-port synchronous SRAM (0.25um) Area: Die size: x um 2 BIST area: 80.1 x um 2 Area overhead : 3.4%

136 mbist1.10Cheng-Wen Wu, NTHU 136 Experimental Results 2K x 32 two-port register file (0.25um) Die size: x um 2 BIST area: x 620 um 2 Area overhead: 4.5%

137 mbist1.10Cheng-Wen Wu, NTHU 137 Why RAM Diagnostics? Memory testing is more and more important Memories are key components Represent about 30% of the semiconductor market Dominate the chip area/yield Memory testing is more and more difficult Growing density, capacity, and speed Emerging new architectures & technologies Growing need for embedded memories Why diagnostics? Yield improvement Repair and/or design/process debugging

138 mbist1.10Cheng-Wen Wu, NTHU 138 Fault Model Subtypes

139 mbist1.10Cheng-Wen Wu, NTHU 139 NTHU-FTC BIST Architecture

140 mbist1.10Cheng-Wen Wu, NTHU 140 Test Mode In Test Mode it runs a fixed algorithm for production test and repair Only a few pins need to be controlled, and BGO reports the result (Go/No-Go)

141 mbist1.10Cheng-Wen Wu, NTHU 141 Fault Analysis Mode In Fault Analysis Mode, we can apply a longer March algorithm for diagnosis FSI captures the error information of the faulty cells EOP format:

142 mbist1.10Cheng-Wen Wu, NTHU 142 Error Catch and Analysis Locate the faulty cells Identify the fault types

143 mbist1.10Cheng-Wen Wu, NTHU 143 How to Identify Fault Type? RAM Circuit/Layout Tester/BIST Output

144 mbist1.10Cheng-Wen Wu, NTHU 144 March Dictionary March 11N E0E0 E 1 E 2 E3E3 E 4 E 5 E 6 E 7 E 8 E 9 E 10

145 mbist1.10Cheng-Wen Wu, NTHU 145 March Signature and Error Map March Signature (Syndrome) Error Map

146 mbist1.10Cheng-Wen Wu, NTHU 146 MECA System

147 mbist1.10Cheng-Wen Wu, NTHU 147 Error Analyzer Data log parser Tester/BIST data log Fault analysis Error maps Fault maps March Dictionary

148 mbist1.10Cheng-Wen Wu, NTHU 148 Fault Analysis Derive analysis equations from the fault dictionary Convert error maps to fault maps by the equations

149 mbist1.10Cheng-Wen Wu, NTHU 149 Test Algorithm Generation Start from a base test: generated by TAGS or user-specified Generation options reduced to read-insertions

150 mbist1.10Cheng-Wen Wu, NTHU 150 Diagnostic Resolution Diagnostic resolution

151 mbist1.10Cheng-Wen Wu, NTHU 151 Experimental Results Proposed diagnosis framework has been applied to commercial embedded SRAMs Results for a 16Kx8 embedded SRAM (FS80A020) are shown Tester log from Credence SC212 is examined Address remapping (logical to physical) is applied

152 mbist1.10Cheng-Wen Wu, NTHU 152 The Total Error Bitmap

153 mbist1.10Cheng-Wen Wu, NTHU 153 Fault Bitmaps Idempotent Coupling FaultStuck-at 0

154 mbist1.10Cheng-Wen Wu, NTHU 154 Redundancy and Repair Problem: We keep shrinking the feature size and increasing the chip density and size. How do we maintain the yield? Solutions: Fabrication Material, process, equipment, etc. Design Device, circuit, etc. Redundancy and repair On-line EDAC (extended Hamming code; product code) Off-line Spare rows and/or columns

155 mbist1.10Cheng-Wen Wu, NTHU 155 From BIST to BISR BISTBISDBIRABISR BIST: built-in self-testBIST: built-in self-test BIECA: built-in error catch & analysisBIECA: built-in error catch & analysis -BISD: built-in self diagnosis -BIRA: built-in redundancy analysis BISR: built-in self-repairBISR: built-in self-repair BIST: built-in self-testBIST: built-in self-test BIECA: built-in error catch & analysisBIECA: built-in error catch & analysis -BISD: built-in self diagnosis -BIRA: built-in redundancy analysis BISR: built-in self-repairBISR: built-in self-repair

156 mbist1.10Cheng-Wen Wu, NTHU 156 RAM Built-In Self-Repair (BISR) RAM MUX BIST Redundancy Analyzer Reconfiguration Mechanism Spare Elements

157 mbist1.10Cheng-Wen Wu, NTHU 157 RAM Redundancy 1-D: spare rows (or columns) only SRAM Algorithm: Must-Repair 2-D: spare rows and columns Local and/or global spares NP-complete problem Conventional algorithm: Must-Repair phase Final-Repair phase Repair-Most (greedy) [Tarr et al., 1984] Fault-Driven (exhaustive, slow) [Day, 1985] Fault-Line Covering (b&b) [Huang et al., 1990]

158 mbist1.10Cheng-Wen Wu, NTHU 158 Redundancy Architectures

159 mbist1.10Cheng-Wen Wu, NTHU 159 An SRAM with BISR [Kim et al., ITC 98]

160 mbist1.10Cheng-Wen Wu, NTHU 160 A DRAM Redundancy Example 4 local spare rows per block 2x4=8 global spare columns

161 mbist1.10Cheng-Wen Wu, NTHU 161 Definitions Faulty line: row or column with at least one faulty cell. A faulty line is covered if all faulty cells in the line are repaired by spare rows and/or columns. A faulty cell not sharing any row or column with any other faulty cell is an orthogonal faulty cell. r: number of (available) spare rows c: number of (available) spare columns F: number of faulty cells in a block F:number of orthogonal faulty cells in a block

162 mbist1.10Cheng-Wen Wu, NTHU 162 Example Block with Faulty Cells

163 mbist1.10Cheng-Wen Wu, NTHU 163 Repair-Most (RM) Run BIST and construct bitmap. Construct row and column error counters. Run Must-Repair algorithm. Run greedy Final-Repair algorithm. Run BIST and construct bitmap. Construct row and column error counters. Run Must-Repair algorithm. Run greedy Final-Repair algorithm.

164 mbist1.10Cheng-Wen Wu, NTHU 164 Worst-Case Bitmap (After Must- Repair) r=2; c=4 Max F=2rc. Max F=r+c. Bitmap size: (rc+c)(cr+r).

165 mbist1.10Cheng-Wen Wu, NTHU 165 Local Repair-Most (LRM) RM is not good enough for embedded RAM. Large storage requirement: bitmap and counters Slow LRM improves the performance. Repair-Most based Improved heuristics Early termination rules Concurrent BIST and BIRA No separate Must-Repair phase LRM reduces the storage required. Smaller local bitmap From (rc+c)x(cr+r) to mxn

166 mbist1.10Cheng-Wen Wu, NTHU 166 LRM Algorithm Activated by BIST whenever a faulty cell is detected. Fault Collection (FC) Collects faulty-cell addresses. Constructs local bitmap. Counts row and column errors. Spare Allocation (SA) Allocate spare rows or columns when bitmap is full. Allocate spare rows or columns at end.

167 mbist1.10Cheng-Wen Wu, NTHU 167 LRM: FC and SA (1,0), (1,6), (2,4), (3,4), (5,1), (5,2)

168 mbist1.10Cheng-Wen Wu, NTHU 168 LRM Example (5,2) (5,4),(5,6),(5,7) (7,3)

169 mbist1.10Cheng-Wen Wu, NTHU 169 Local Optimization (LO) LMR has drawbacks: Selecting line with largest fault count may be slow. Multiple lines may need to be selected for repair. Area overhead is still high. Repair rate depends on bitmap size. LO has a better repair rate based on same hardware overhead, i.e., a higher repair efficiency. Fault Collection (FC) Records faulty cells in bitmap until it is full. Spare Allocation (SA) Exhaustive search performed for repairing all faults. Bitmap cleared; process repeated until done.

170 mbist1.10Cheng-Wen Wu, NTHU 170 LO: Column*/Row Selection for SA A 1 means that the corresponding col is selected for repair, unless empty. A 1 means that the corresponding col is selected for repair, unless empty. * Assume column selection has a lower cost than row selection. Col selection vector 1. Col 5 selected for repair. Row selection vector 2. Row 5 is selected for repair.

171 mbist1.10Cheng-Wen Wu, NTHU 171 LO Example

172 mbist1.10Cheng-Wen Wu, NTHU 172 Essential Spare Pivoting (ESP) Maintain high repair rate without using a bitmap. Small area overhead. Fault Collection (FC) Collect and store faulty-cell address using row- pivot and column-pivot registers. If there is a match for row (col) pivot, the pivot is an essential pivot. If there is no match, store the row/col addresses in the pivot registers. If F > r+c, the RAM is unrepairable. Spare Allocation (SA) Use row and column pivots for spare allocation. Spare rows (cols) for essential row (col) pivots. SA for orthogonal faults.

173 mbist1.10Cheng-Wen Wu, NTHU 173 ESP Example

174 mbist1.10Cheng-Wen Wu, NTHU 174 Cell Fault Size Distribution Mixed Poisson-exponential distribution.

175 mbist1.10Cheng-Wen Wu, NTHU 175 Repair Rate Comparison 1,552 RAM blocks. 1,024 x 64 bits per block. r from 6 to 10. c from 2 to 6. LRM bitmap: r x c. LO bitmap: 8 x 4. 1,552 RAM blocks. 1,024 x 64 bits per block. r from 6 to 10. c from 2 to 6. LRM bitmap: r x c. LO bitmap: 8 x 4.

176 mbist1.10Cheng-Wen Wu, NTHU 176 Normalized Repair Rate

177 mbist1.10Cheng-Wen Wu, NTHU 177 Repair Rate (r=10)

178 mbist1.10Cheng-Wen Wu, NTHU 178 Normalized Repair Rate (r=6)

179 mbist1.10Cheng-Wen Wu, NTHU 179 Area Overhead Overhead is about 5-12% for 16Mb DRAM, r=8, and c=4.

180 mbist1.10Cheng-Wen Wu, NTHU 180 Computation Time (Simulated)

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