We think you have liked this presentation. If you wish to download it, please recommend it to your friends in any social system. Share buttons are a little bit lower. Thank you!
Presentation is loading. Please wait.
Published byKaleigh Lamm
Modified over 2 years ago
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation Contact Reinier A. van Mourik, MSc PhD Researcher Spintronics Devices IBM / Eindhoven University of Technology IBM Almaden Research Center 650 Harry Rd San Jose, CA USA Tel Fax Mobile
© 2009 IBM Corporation Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation Reliability of Signal Propagation in Magnetostatically Coupled Arrays of Magnetic Nanoelements Reinier van Mourik 1,2, Li Gao 1, Brian Hughes 1, Charles Rettner 1, Bert Koopmans 2, Stuart Parkin 1 1. IBM Almaden Research Center, San Jose, CA 2. Eindhoven University of Technology, Eindhoven, the Netherlands
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 1. Introduction Nanomagnetic logic - principle Energy-efficient Non-volatile Fast Radiation resistant Majority gate A BD C M A B C D M Majority gate is programmable NAND/NOR gate Full logic set output read
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 1. Introduction Outline Experiment and simulation: inherent unreliability Alternative for conventional NML: Domain wall clocking
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Experiment setup fabrication measurement Artificial input biases first dot according to reset direction ~70Oe d514 MFM shows state of each dot The RH curve of the MTJ shows output of device
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Single device: shot-to-shot results Output MTJ state alternates accordingly when alternating input direction. input output
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Many devices: device-to-device results Success/error is highly reproducible, thus inherent in device. 68/158 (43%) of devices contain errors repeat clocking cycle, input +x clocking cycle, input +x clocking cycle, input -x 116/123 (94%) of devices evolve to exact same state 66/79 (84%) of devices evolve to exact inverse state
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 2. Error rate in NML devices Error rate in signal propagation - simulations Device-to-device error rate tends to 50% as length increases Last NM evolves before signal reaches it Errors are caused by last magnet evolving early.
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking Domain wall clocking - principle Fringing field from domain wall in perpendicularly magnetized material can reset nanomagnets.
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking DW clocking – experimental setup PMA nanowire nm wide Domain wall injection line Hall bar nanodots Py 60x90x20nm AMR read hall bar read DW 1. inject DW 2. propagate DW by H field 3. read resistance change in AMR and Hall bar
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation 3. Domain wall clocking DW clocking - results Prepare device in incorrect state Pass DW underneath End in correct state DW clocking demonstrated in 1- and 2-magnet devices
IBM Research Nanomagnetic Logic | Mar | IBM/TUe © 2013 IBM Corporation Conclusion Nanomagnetic Logic is magnetic alternative to CMOS logic Analysis done of reliability of NML devices with integrated output Errors are reproducible per device and tend to 50% among devices. Domain Wall clocking is demonstrated as alternative clocking scheme slides & contact:
© 2009 IBM Corporation MMM 2013 | | IBM/TUe © 2013 IBM Corporation Domain wall pinning dependent on nanomagnet state Reinier van Mourik 1,2,
NSC-2 Hybrid Hall Effect Devices -- a Novel Building Block for Reconfigurable Logic Steve Ferrera, Nicholas P. Carter University of Illinois at Urbana-Champaign.
NANOCOMPUTING BY FIELD-COUPLED NANOMAGNETS n AUTHORS : Gyorgy Csaba Alexandra Imre Gary H. Bernstein Wolfang Porod (fellow IEEE) Vitali Metlushko n REFERENCE.
Nanomagnetic structures for digital logic Russell Cowburn Durham University Physics Department, UK
1 Giant Magneto-Resistive Switches & Spin Torque Transfer Switches friendly critic analysis ERD "Beyond CMOS" Technology Maturity Evaluation Workshop San.
EE698A Advanced Electron Devices Magnetic sensors and logic gates Ling Zhou EE698A.
Gated Hybrid Hall Effect (HHE) devices on silicon Pratyush Das Kanungo, Alexandra Imre, Wu Bin, Alexei Orlov, Greg Snider, Wolfgang Porod Dept of Electrical.
Advanced Computing and Information Systems laboratory Device Variability Impact on Logic Gate Failure Rates Erin Taylor and José Fortes Department of Electrical.
ITRS Emerging Logic Device working group George Bourianoff, Intel San Francisco, Ca July 10, 2011 April 10, ERD Meeting Potsdam, Germany 1.
Lab 08: SR Flip Flop Fundamentals: Slide 2 Slide 3 NOR Gate SR Flip Flop. SR Flip Flop. Slide 4 SR Flip Flop with a positive edge clock: Slide 5 SR Flip.
Ch. 7 Memory and Programmable Logic. Random-Access Memory Memory Decoding Error Detection and Correction Read-Only Memory Programmable Logic.
Q R Flip Flops ATS 電子部製作 S Q For a NOR gate, the output would be logic 1 only when both the inputs are 0 : AB F A B F.
G. Csaba, A. Csurgay, P. Lugli and W. Porod University of Notre Dame Center for Nano Science and Technology Technische Universit ä t M ü nchen Lehrst ü.
1. 2 Collaborators EXPERIMENT Duc Nguyen, 3 rd year student UNM/AFRL RVSE Camron Kouhestani, 3 rd year student UNM/AFRL RVSE Rod Devine, Think Strategically/AFRL.
Lecture 21, Slide 1EECS40, Fall 2004Prof. White Lecture #21 OUTLINE –Sequential logic circuits –Fan-out –Propagation delay –CMOS power consumption Reading:
CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to CMOS Complementary Metal-Oxide Semiconductor.
A Programmable Logic Device Lecture 4.3. A Programmable Logic Device Multiple-input Gates A 2-Input, 1-Output PLD.
DSD Presentation Introduction of Actel FPGA. page 22015/9/11 Presentation Outline Overview Actel FPGA Characteristic Actel FPGA Architecture Actel.
Robot and Servo Drive Lab. Department of Electrical Engineering Southern Taiwan University of Science and Technology Advanced Servo Control 12/24/2014.
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
Principles of Physics Electromagnetic Induction. Changing magnetic fields can create a voltage (and thus cause current to flow) in a conductor A wire.
CMOS Logic. The CMOS Logic uses a combination of p-type and n-type Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) to implement logic gates.
MAPLD 2005/213Kakarla & Katkoori Partial Evaluation Based Redundancy for SEU Mitigation in Combinational Circuits MAPLD 2005 Sujana Kakarla Srinivas Katkoori.
MOS-AK avril 2005 CMOS compatible integrated magnetometers L. Hébrard 1, J.-B. Kammerer 1, M. Hehn 2, V. Frick 1, A. Schuhl 2, P. Alnot 3, P. French.
DIGITAL SYSTEMS ECE-273, Digital Systems Dr. Herb Kaufman Electrical and Computer Engineering UofM-Dearborn 1.
Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration Adrian Stoica Ricardo S.
FPGA Configuration. Introduction What is configuration? – Process for loading data into the FPGA Configuration Data Source Configuration Data Source FPGA.
Adopting Multi-Valued Logic for Reduced Pin-Count Testing Baohu Li, Bei Zhang and Vishwani Agrawal Auburn University, ECE Dept., Auburn, AL 36849, USA.
1 Chapter 3 Logic Gates. 2 Inverter 3 Inverter Truth Table.
Abdullah Aldahami ( ) Feb26, Introduction 2. Feedback Switch Logic 3. Arithmetic Logic Unit Architecture a.Ripple-Carry Adder b.Kogge-Stone.
Logic Gates. AND Function Output Y is TRUE if inputs A AND B are TRUE, else it is FALSE. Logic Symbol Text Description Truth Table Boolean Expression.
An Image Filtering Technique for SPIDER Visible Tomography N. Fonnesu M. Agostini, M. Brombin, R.Pasqualotto, G.Serianni 3rd PhD Event- York- 24th-26th.
Kandemir224/MAPLD Reliability-Aware OS Support for FPGA-Based Systems M. Kandemir, G. Chen, and F. Li Department of Computer Science & Engineering.
GaAs radiation imaging detectors with an active layer thickness up to 1 mm. D.L.Budnitsky, O.B.Koretskaya, V.A. Novikov, L.S.Okaevich A.I.Potapov, O.P.Tolbanov,
University of Notre Dame Lecture 19 - Intro to MQCA Nanomagnetic Logic Devices.
Electronic Counters. Abstract Electronic counters come in two flavors: asynchronous and synchronous. Asynchronous counter encode a count sequence by directly.
Programmable Logic PAL, PLA. 2 PLAs Programmable Logic Array Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/
Introduction to Quantum Computing By Sumant Gupta C.S.E.
Acknowledgments: Interfacing ultracold atoms with nanomagnetic A. D. West 1, K. J. Weatherill 1, T. Hayward 2, D. Allwood 2 and I. G. Hughes 1 1 Joint.
Combinational Logic Logic gates. and, or, not Derived gates. nand, nor, xor John F. Wakerly – Digital Design. 4 th edition. Chapter 4.
LOGIC GATES Logic generally has only 2 states, ON or OFF, represented by 1 or 0. Logic gates react to inputs in certain ways. Symbol for AND gate INPUT.
Introduction to CMOS VLSI Design Lecture 5: Logical Effort GRECO-CIn-UFPE Harvey Mudd College Spring 2004.
Montek Singh COMP Sep 6, Basics of magnetism Nanomagnets and their coupling Next class: ◦ Challenges and Benefits ◦ Open questions.
Lecture 2 Universal Gates Sum of Products Products of Sum.
Reliable Data Processor in VLSI Senior Capstone Project Presented By Rahul Chopra May 7th 2002 Advisor: Dr. Vinod Prasad Abstract: The Reliable Data Processor.
Lab 04 :Serial Data Control Systems : Slide 2 Slide 3 Slide 4 NOR Gate: NAND Gate: NOR / NAND Alternate Symbols: Slide 5 XOR and XNOR Gate: Serial Data.
Bayesian Macromodeling for Circuit Level QCA Design Saket Srivastava and Sanjukta Bhanja Department of Electrical Engineering University of South Florida,
SRAM Design for SPEED GROUP 2 Billy Chantree Daniel Sosa Justin Ferrante.
Introduction to Computing Systems from bits & gates to C & beyond Chapter 3 Digital Logic Structures Transistors Logic gates & Boolean logic Combinational.
The Digital Logic Level Computer Organization Lecture #6 Jahan Zeb.
© 2016 SlidePlayer.com Inc. All rights reserved.