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Programmable Logic Devices and Architectures: A Nano-Course R. Katz Grunt Engineer NASA.

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Presentation on theme: "Programmable Logic Devices and Architectures: A Nano-Course R. Katz Grunt Engineer NASA."— Presentation transcript:

1 Programmable Logic Devices and Architectures: A Nano-Course R. Katz Grunt Engineer NASA

2 What We Will Cover Various programmable logic types Device architectures Device performance Packaging Reliability Some radiation considerations Lessons learned

3 What You Will Not Learn You will not learn much. This course is only a brief introduction to key concepts and issues, not a comprehensive and in-depth tutorial. Because of time limitations, sections have been either scaled back or eliminated.

4 References References are available for most slides Original work –available on Manufacturers data sheets, application notes Papers and reports –Many from MAPLD 1998, 1999, 2000 Standard logic design textbooks

5 Lessons Learned (1) Barto's Law: Every circuit is considered guilty until proven innocent.

6 Lessons Learned (2) Launched: March 4, 1999 Failed: March 4, 1999

7 Applications Some Application Types Existing SSI/MSI Integration Obsolete/"Non-Space-Qualified" Component Replacement Bus Controllers/Interfaces Memory Controller/Scrubber High-Performance DSP Processors Systems on Chip Many Other Digital Circuits

8 SSI/MSI Logic Integration

9 Non-Space Qual Microcontroller

10 Complex System-on-Chip SSTL Core ESA Core Debug CAN Network>100Mbps 170Mbyte Microdrive TX TCSP 1M*64 SRAM CANBUS LVDS RX2RX1RX0 Linear Regulator POR +3.3V EDAC DECDED ROM LUT Bootstrap AMBA AHB CAN Interface AMBA AHB LEON Sparc V8 CORDIC Coprocessor AMBA AHB HDLC TX Controller AMBA AHB HDLC RX Controller FIFO AMBA AHB HDLC RX Controller FIFO AMBA AHB HDLC RX Controller FIFO System Bus CF+ I/F True IDE FIFO Parallel Port Interface UART AMBA AHB PIO FIFO AMBA AHB +2.5V+3.3V CLK

11 Programmable Elements Overview Antifuse –ONO and Metal-to-Metal (M2M) –Construction –Resistance SRAM –Structure –Quantity EEPROM/Flash Ferroelectric Memory Summary of Properties

12 Antifuse Technology ONO Antifuse (Actel) Poly/ONO/N++ Heavy As doped Poly/N++ Thickness controlled by CVD nitride Programs ~ 18V Typical Toxono ~ 85 Å Hardened Toxono ~ 95 Å R = ohms thermal oxide CVD nitride thermal oxide FOX N++ Polysilicon ONO Metal-to-Metal Antifuse (Actel, UTMC, Quicklogic) Pancake Stack Between Metal Layers Used in 3.3V Operation in Sea Of Gates FPGA Other devices (as shown later) Program at ~ 10V Typical thickness ~ Å R = ohms Metal - 3 Top Electrode Amorphous Silicon Dielectric (optional) Metal - 2 Bottom Electrode

13 Antifuse Cross-Sections Amorphous Silicon (Vialink) ONO (Act 1)

14 M2M = Metal-to-metal M2M Antifuse in Multi-layer Metal Process SX, SX-A, and SX-S Vialink

15 Programmed Antifuse Resistance Distributions The resistance of programmed antifuses is stable with temperature, varying less than 15 percent per 100°C.

16 SRAM Switch Technology Read or Write Data Configuration Memory Cell Routing Connections

17

18 Summary of Current Technology Type Re-programmable Volatile Technology Radiation Hardness Fuse No No Bipolar Hard EPROM Yes No UVCMOS Moderate EEPROM YES, ICP No EECMOS Moderate SRAM YES, ICP Yes CMOS Soft Antifuse No No CMOS+ Hard FRAM Yes, ICP No Perovskite Hard 1 Ferroelectric Crystal 1 Get Bennedetto paper to verify.

19 FPGA Architecture Assembly of Fundamental Blocks –Hierarchical –Integration of Different Building Blocks Logic (Combinational and Sequential) Dedicated Arithmetic Logic Clocks Input/Ouput Delay Locked Loop RAM Routing (Interconnections) –Channeled Architecture –Sea-of-Module Architecture

20 Channel Architecture

21 Channeled Routing Structure Programmed Antifuse Horizontal Track Vertical Track Modules Unprogrammed Antifuse Modules Horizontal Control

22 Act 3 Architecture Detail

23 Sea-of-Modules Structure Some programmable elements require silicon resources –SRAM flip-flops –ONO antifuse Metal-to-metal antifuses are built above the logic –No routing channels –Higher density –Faster

24 UT4090 Architecture RAM Blocks Logic Array RAM Blocks

25 Virtex Architecture Overview IOB = I/O Block DLL = Delay-locked loop BRAM = Block RAM (4,096 bits ea.) CLB = Configurable Logic Block

26 Two Slice Virtex CLB

27 Logic Modules Actel (Act 1,2,3, SX) –Basics –Flip-flop Construction UTMC/Quicklogic (i.e., UT4090) –RAM blocks Xilinx (i.e., CQR40xxXL, Virtex) –LUTs/RAM –Carry Logic/Chain Mission Research Corp. (MRC) - Orion Atmel - AT6010

28 Act 2 Logic Module: C-Mod 8-Input Combinational function 766 possible combinational macros 1 1 Antifuse Field Programmable Gate Arrays, J. Greene, E. Hamdy, and S. Beal, Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp

29 Act 2 Flip-flop Implementation Hard-wired Flip-flop Feedback goes through antifuses (R) and routing segments (C) Routed or C-C Flip-flop

30 SX-S R-Cell Implementation

31 UT4090 Logic Module Antifuse Configuration Memory Mux-based Multiple Outputs Wide logic functions

32 UT4090 RAM Module Dual-port 1152 bits per cell Four configurations –64 X 18 –128 X 9 –256 X 4 –512 X 2

33 XC4000 Series CLB Simplified CLB - Carry Logic Not Shown RAM LUTs for Logic or small SRAM Two Flip-flops

34 XQR4000XL Carry Path General interconnect Placement is important for performance.

35 Carry Logic Operation Effective Carry Logic for a Typical Addition - XQR4000XL

36 MRC Orion Logic Module

37 AT60xx Logic Module

38 Memory Architecture Radiation-hardened PROM Configuration memory EEPROM

39 Rad-Hard PROM Architecture No latches in this architecture

40 Configuration PROM Example

41 W28C64 EEPROM Simplified Block Diagram Row Address Latches Column Address Latches A 6-12 A 0-5 Row Address Decoder Column Address Decoder Edge Detect & Latches Control Latch Control Logic CE* WE* OE* 64 Byte Page Buffer Timer CLK E 2 Memory Array I/O Buffer/ Data Polling I/O 0-7 Latch Enable PERSTB VW

42 Input/Output Modules A Brief Overview Basic Input/Output (I/O) Module Some Features –Slew Rate Control –Different I/O Standards –Input Delays –Banks Deterministic Powerup Cold Sparing

43 Act 1 Many families have slew rate control to limit signal reflections and ground bounce. Different families drive their outputs to different levels.

44 Different I/O Standards Virtex 2.5V Example I/O Standard Input Ref Output Board 5V Voltage Source Termination Tolerant (V REF ) Voltage Voltage (V CCO ) (V TT ) LVTTL 2–24 mA N/A 3.3 N/A Yes LVCMOS2 N/A 2.5 N/A Yes PCI, 5 V N/A 3.3 N/A Yes PCI, 3.3 V N/A 3.3 N/A No GTL 0.8 N/A 1.2 No GTL+ 1.0 N/A 1.5 No HSTL Class I No HSTL Class III No HSTL Class IV No SSTL3 Class I &II No SSTL2 Class I & II No CTT No AGP N/A No

45 Virtex 2.5V

46 Deterministic Power-up SX-S Example PRE CLR V CCI RTSX-S Input Driven low or external POR Signal Pull-down enabled Pull-up enabled Pull-ups /downs are selectable on an individual I/O basis Pull-up follows V CCI Pull-downs and pull-ups are dis- abled 50 ns after V CCA reaches 2.5V and therefore do not draw current during regular operation. Once V CCA is powered-up, 50ns is required for a valid signal to propagate to the outputs before the pull-ups /downs are disabled V CCA

47 Cold Sparing - SX-S RTSX-S V CCI GND 0 Volts RTSX-S V CCI GND 3.3/5 Volts Active Bus or Backplane Powered-down Board Powered-up Board I/O w/ Hot-Swap Enabled does not sink current

48 Packaging and Mechanical Aspects Package Types –Dual In-line Package (DIPs) –Flatpacks –Pin Grid Arrays (PGAs) –Ceramic Quad Flat Packs (CQFP) –Plastic Quad Flat Pack (PQFP) Plastic Package Qualification Lead/Ball Pitch Mass Characteristics Shielding

49 Flat Pack Northrop-Grumman 256k EEPROM

50 Shielded Packages - Rad-Pak This package, with tie bar, 24 grams Shielding thickness may vary between lots Shield is 10-90/copper-tungsten Density of shield is ~ 18 g/cm 3 (need to verify) EEPROMs and other devices also packaged similarly

51 Spot Shielding Qualification Board - Maximum Thickness

52 PGA Packages (cont'd)

53 PQFP Package

54 Nominal Lead/Ball Pitch CQ " CQ " CQ " CQ " CQ mm PQ mm CQ mm CG mm Note: Pin spacing for PGAs is typically 0.1"

55 Mass Characteristics Approximate values (in grams) CQ CQ CQ CQ CQ CQ PQ CB CQ CQ With heat sink. Over the years, there has been a lot of variation as to which parts have heat sinks. Check each package. PG PG PG PG PG BG CG

56 Reliability Introduction to Reliability Historical Perspective Current Devices Trends

57 The Bathtub Curve Time Failure rate, Constant Useful lifeWear out Infant Mortality

58 Introduction to Reliability Failure in time (FIT) Failures per 10 9 hours ( ~ 10 4 hours/year ) Acceleration Factors –Temperature –Voltage

59 Introduction to Reliability (cont'd) Most failure mechanisms can be modeled using the Arrhenius equation. ttf - time to failure (hours) C - constant (hours) E A - activation energy (eV) k - Boltzman's constant (8.616 x eV/°K) T - temperature (ºK) ttf = C e E A /kT

60 Integrated Circuit Reliability Historical Perspective Application Reliability Apollo Guidance Computer < 10 FITs Commercial (1971) 500 Hours Military (1971) 2,000 Hours High Reliability (1971) 10,000 Hours SSI/MSI/PROM (1976) FITs MSI/LSI CICD Hi-Rel (1987) 43 FITs

61 Actel FPGAs Technology FITS # Failures Device-Hours ( m) 2.0/ x x x x x x 10 7 RTSX x x x 10 7

62 Xilinx FPGAs XC40xxXL –Static: 9 FIT, 60% UCL –Dynamic: 29 FIT, 60% UCL XCVxxx –Static: 34 FIT, 60% UCL –Dynamic: 443 FIT, 60% UCL

63 UTMC and Quicklogic FPGA –< 10 FITS (planned) –Quicklogic reports 12 FIT, 60% UCL UT22VP10 UTER Technology, 0 failures, 0.3 [double check] Antifuse PROM – 64K: 19 FIT, 60% UCL –256K: 76 FIT, 60% UCL

64 Actel FIT Rate Trends

65 Thermal Thermal Analysis Basics Summary of Package Characteristics Package Considerations –Cavity Up/Down –Heat Sinks

66 Thermal Performance Package modeled as a resistance Junction temperature the critical parameter –Often derated to ~ 100 ºC t J = P J-C t J = Junction temperature in ºC P = Power in watts J-C = thermal resistance, junction to case, in ºC/watt

67 Thermal Performance - Devices J-C for Flight Devices in ºC/watt Ceramic Pin Grid Array PG PG PG PG PG Notes: 1 These packages are cavity down. 2 With embedded heat spreader 3 Estimated 4 Typical Ceramic Quad Flat Pack CQ CQ CQ CQ CQ CQ Other PQ /3.8 2 PQ HQ CG

68 Die Up or Down?

69 CQFP256 w/ Heat Sink

70 Speed/Performance Basic Delay Model and Components Sample Delays –Examples from different families Hard-wired Structures –Routing –Arithmetic Logic

71 Antifuse Delay Model Tau = Resistance * Capacitance

72 Note: These numbers are approximate and work on better numbers is in progress. UTMC, for PAL and PROM, has about 8 to 10 fF.

73

74 Hardwired Structures Actel Routing Model Direct Connect Fast Connect (ns) (ns) RT54SX RT54SXS Virtex Carry Chain T BYP (C IN to C OUT) 200 ps, max

75 Power Consumption Power Basics Quiescent (Static) Current Dynamic Current –Per logic module –Clock tree

76 Power - Basics Power = Voltage * current = V i Voltage is constant Current = Static + Dynamic Static current: leakage, pullup resistors, DC loads Dynamic Power = kv 2 f k: constant often referred to as C EQ f: frequency

77

78 Device (Array) Quiescent Current 1 Device Voltage Typical Spec Level Type (V) I CC (mA) I CCMAX (mA) A500K < Orion-4K 5.0 RT < 1 20 RT1280A 5.0 < 1 20 RT14100A 5.0 < 1 20 RT54SX < 1 25 RT54SX32S 2.5 < 1 25 UT XQR40xxXL XQV XQV XQV XQV AT No DC Loads 2 Commercial Specification XQV600 Lot Data (mA) 1 lot # min mean max commercial or industrial worst-case, checking

79 PROM Device Current 1 Device Voltage Standby (MHz) Type (V) I CC (mA) I CCMAX (mA) UT28F UT28F < A Specification levels mA/MHz 3 BAE Systems (formerly Lockmart) 32kx8 PROM

80 Representative Dynamic Power Numbers A1280/A1280XL Power (mW) F(MHz) Module Input Output Clock Total , , ,087 2,879

81 Preliminary

82 A Brief Introduction to Radiation and Programmable Devices

83 Types of Radiation Effects Total Dose Single Event Effects (SEE) –Single Event Upset (SEU) Multiple Bit Upset (MBU) –Single Event Latchup (SEL) –Single Event Transient (SET) –Antifuse and Rupture –Loss of Functionality –Snap back Protons Miscellaneous

84 Total Dose

85 Recombination, Transport, and Trapping of Carries

86 Typical TID Run

87 TID Run - Runaway

88 TID Capability vs. Feature Size

89 Process Mods m

90 Single Event Upset (SEU)

91 From Aerospace

92 Cross Section versus LET Curve From Aerospace

93 Act 2 SEU Flip-Flop Data

94 XQR4036XL SEU Cross Section From Lum

95 Single Event Latchup (SEL)

96 Latchup Basics From Harris

97 SEL - QL m BNL 02/98 S/N QL1 Run T2 V BIAS = 5.0V, 3.3V 0 Deg LET = 18.8 MeV-cm 2 /mg

98 Antifuse and Rupture

99 ONO Antifuse Technology Development Vehicle Comparison of Rupture Currents Amorphous Silicon Antifuse Rupture

100 Mag = 5X Mag = 20X Mag = 100X ONO Antifuse Breakdown - FA

101 Protons

102 I CC Damage During Proton Testing ASIC and Antifuse FPGA Note: Different scales for each run.

103 RH1280 Proton Upsets From Lockheed-Martin/Actel

104 Summary and Some Words of Wisdom

105 FRAM Memory Functionality Loss During Heavy Ion Test Strip chart of FM1608 (research fab) current during heavy ion irradiation. The device lost functionality during the test while the current decreased from it's normal dynamic levels of approximately 6.3 mA to it's quiescent value, near zero. The device recovered functionally and operated normally throughout the latter part of the test. This effect was seen at least three times during the limited testing of this device.


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