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Programmable Logic Devices and Architectures: A Nano-Course

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Presentation on theme: "Programmable Logic Devices and Architectures: A Nano-Course"— Presentation transcript:

1 Programmable Logic Devices and Architectures: A Nano-Course
R. Katz Grunt Engineer NASA

2 What We Will Cover Various programmable logic types
Device architectures Device performance Packaging Reliability Some radiation considerations Lessons learned

3 What You Will Not Learn You will not learn much. This course is only a brief introduction to key concepts and issues, not a comprehensive and in-depth tutorial. Because of time limitations, sections have been either scaled back or eliminated.

4 References References are available for most slides Original work
available on Manufacturers’ data sheets, application notes Papers and reports Many from MAPLD 1998, 1999, 2000 Standard logic design textbooks

5 Barto's Law: Every circuit is considered guilty until proven innocent.
Lessons Learned (1) Barto's Law: Every circuit is considered guilty until proven innocent.

6 Lessons Learned (2) Launched: March 4, 1999 Failed: March 4, 1999

7 Applications Some Application Types
Existing SSI/MSI Integration Obsolete/"Non-Space-Qualified" Component Replacement Bus Controllers/Interfaces Memory Controller/Scrubber High-Performance DSP Processors Systems on Chip Many Other Digital Circuits

8 SSI/MSI Logic Integration

9 Non-Space Qual Microcontroller

10 Complex System-on-Chip
RX0 CLK RX1 CLK RX2 CLK TX CLK CAN Network >100Mbps CAN BUS LVDS POR HDLC RX Controller HDLC RX Controller HDLC RX Controller HDLC TX Controller Parallel Port Interface CAN Interface FIFO FIFO FIFO FIFO FIFO AMBA AHB AMBA AHB AMBA AHB AMBA AHB AMBA AHB AMBA AHB System Bus AMBA AHB AMBA AHB AMBA AHB LEON Sparc V8 CORDIC Coprocessor ROM LUT Bootstrap EDAC DECDED CF+ I/F True IDE PIO UART +2.5V +3.3V SSTL Core ESA Core Linear Regulator 1M*64 SRAM SP TC Debug 170Mbyte Microdrive +3.3V

11 Programmable Elements Overview
Antifuse ONO and Metal-to-Metal (M2M) Construction Resistance SRAM Structure Quantity EEPROM/Flash Ferroelectric Memory Summary of Properties

12 Antifuse Technology ONO Antifuse (Actel) Metal-to-Metal Antifuse
Polysilicon ONO Metal - 3 Top Electrode Amorphous Silicon FOX N++ Dielectric (optional) thermal oxide Metal - 2 Bottom Electrode CVD nitride thermal oxide ONO Antifuse (Actel) Poly/ONO/N++ Heavy As doped Poly/N++ Thickness controlled by CVD nitride Programs ~ 18V Typical Toxono ~ 85 Å Hardened Toxono ~ 95 Å R = ohms Metal-to-Metal Antifuse (Actel, UTMC, Quicklogic) ‘Pancake’ Stack Between Metal Layers Used in 3.3V Operation in Sea Of Gates FPGA Other devices (as shown later) Program at ~ 10V Typical thickness ~ Å R = ohms

13 Antifuse Cross-Sections
ONO (Act 1) Amorphous Silicon (Vialink)

14 M2M Antifuse in Multi-layer Metal Process
SX, SX-A, and SX-S Vialink M2M = Metal-to-metal

15 Programmed Antifuse Resistance Distributions
The resistance of programmed antifuses is stable with temperature, varying less than 15 percent per 100°C.

16 SRAM Switch Technology
Configuration Memory Cell Read or Write Data Routing Connections


18 Summary of Current Technology
Type Re-programmable Volatile Technology Radiation Hardness Fuse No No Bipolar Hard EPROM Yes No UVCMOS Moderate EEPROM YES, ICP No EECMOS Moderate SRAM YES, ICP Yes CMOS Soft Antifuse No No CMOS Hard FRAM Yes, ICP No Perovskite Hard1 Ferroelectric Crystal 1Get Bennedetto paper to verify.

19 FPGA Architecture Assembly of Fundamental Blocks
Hierarchical Integration of Different Building Blocks Logic (Combinational and Sequential) Dedicated Arithmetic Logic Clocks Input/Ouput Delay Locked Loop RAM Routing (Interconnections) Channeled Architecture Sea-of-Module Architecture

20 Channel Architecture

21 Channeled Routing Structure
Modules Unprogrammed Antifuse Programmed Antifuse Horizontal Track Modules Vertical Track Horizontal Control

22 Act 3 Architecture Detail

23 Sea-of-Modules Structure
Some programmable elements require silicon resources SRAM flip-flops ONO antifuse Metal-to-metal antifuses are built above the logic No routing channels Higher density Faster

24 UT4090 Architecture RAM Blocks Logic Array RAM Blocks

25 Virtex Architecture Overview
IOB = I/O Block DLL = Delay-locked loop BRAM = Block RAM (4,096 bits ea.) CLB = Configurable Logic Block

26 Two Slice Virtex CLB

27 Logic Modules Actel (Act 1,2,3, SX) UTMC/Quicklogic (i.e., UT4090)
Basics Flip-flop Construction UTMC/Quicklogic (i.e., UT4090) RAM blocks Xilinx (i.e., CQR40xxXL, Virtex) LUTs/RAM Carry Logic/Chain Mission Research Corp. (MRC) - Orion Atmel - AT6010

28 Act 2 Logic Module: C-Mod
8-Input Combinational function 766 possible combinational macros1 1”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal, Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp

29 Act 2 Flip-flop Implementation
Feedback goes through antifuses (R) and routing segments (C) Hard-wired Flip-flop Routed or “C-C Flip-flop”

30 SX-S R-Cell Implementation

31 UT4090 Logic Module Antifuse Configuration Memory Mux-based
Multiple Outputs Wide logic functions

32 UT4090 RAM Module Dual-port 1152 bits per cell Four configurations
64 X 18 128 X 9 256 X 4 512 X 2

33 XC4000 Series CLB Simplified CLB - Carry Logic Not Shown
RAM LUTs for Logic or small SRAM Two Flip-flops

34 Placement is important for performance.
XQR4000XL Carry Path Placement is important for performance. General interconnect

35 Carry Logic Operation Effective Carry Logic for a Typical Addition - XQR4000XL

36 MRC Orion Logic Module

37 AT60xx Logic Module

38 Memory Architecture Radiation-hardened PROM Configuration memory

39 Rad-Hard PROM Architecture
No latches in this architecture

40 Configuration PROM Example

41 W28C64 EEPROM Simplified Block Diagram
Memory Array Row Address Latches Row Address Decoder A6-12 Column Address Latches Column Address Decoder 64 Byte Page Buffer A0-5 Edge Detect & Latches CE* Timer WE* I/O Buffer/ Data Polling Latch Enable Control Latch Control Logic OE* CLK VW I/O0-7 PE RSTB

42 Input/Output Modules A Brief Overview
Basic Input/Output (I/O) Module Some Features Slew Rate Control Different I/O Standards Input Delays Banks Deterministic Powerup Cold Sparing

43 Act 1 Many families have slew rate control to limit signal reflections and ground bounce. Different families drive their outputs to different levels.

44 Different I/O Standards Virtex 2.5V Example
I/O Standard Input Ref Output Board V Voltage Source Termination Tolerant (VREF) Voltage Voltage (VCCO) (VTT) LVTTL 2–24 mA N/A N/A Yes LVCMOS N/A N/A Yes PCI, 5 V N/A N/A Yes PCI, 3.3 V N/A N/A No GTL N/A No GTL N/A No HSTL Class I No HSTL Class III No HSTL Class IV No SSTL3 Class I &II No SSTL2 Class I & II No CTT No AGP N/A No

45 Virtex 2.5V

46 Deterministic Power-up SX-S Example
VCCA VCCI Pull-ups /downs are selectable on an individual I/O basis Pull-up follows VCCI Pull-downs and pull-ups are dis- abled 50 ns after VCCA reaches 2.5V and therefore do not draw current during regular operation. Once VCCA is powered-up, 50ns is required for a valid signal to propagate to the outputs before the pull-ups /downs are disabled RTSX-S Pull-up enabled PRE Input Driven low or external POR Signal CLR Pull-down enabled

47 Cold Sparing - SX-S Powered-up 3.3/5 Volts Powered-down Board 0 Volts
RTSX-S VCCI GND 0 Volts 3.3/5 Volts Active Bus or Backplane Powered-down Board Powered-up I/O w/ ” Hot-Swap” Enabled does not sink current

48 Packaging and Mechanical Aspects
Package Types Dual In-line Package (DIPs) Flatpacks Pin Grid Arrays (PGAs) Ceramic Quad Flat Packs (CQFP) Plastic Quad Flat Pack (PQFP) Plastic Package Qualification Lead/Ball Pitch Mass Characteristics Shielding

49 Flat Pack Northrop-Grumman 256k EEPROM

50 Shielded Packages - Rad-Pak™
This package, with tie bar, 24 grams Shielding thickness may vary between lots Shield is 10-90/copper-tungsten Density of shield is ~ 18 g/cm3 (need to verify) EEPROMs and other devices also packaged similarly

51 Spot Shielding Qualification Board - Maximum Thickness

52 PGA Packages (cont'd)

53 PQFP Package

54 Nominal Lead/Ball Pitch
CQ " CQ " CQ " CQ " CQ mm PQ mm CQ mm CG mm Note: Pin spacing for PGAs is typically 0.1"

55 Mass Characteristics Approximate values (in grams)
CQ CQ CQ CQ CQ CQ PQ CB CQ CQ PG PG PG PG PG 1 BG CG 1 1With heat sink. Over the years, there has been a lot of variation as to which parts have heat sinks. Check each package.

56 Reliability Introduction to Reliability Historical Perspective
Current Devices Trends

57 The Bathtub Curve Time Failure rate,   Constant Useful life Wear out
Infant Mortality

58 Introduction to Reliability
Failure in time (FIT) Failures per 109 hours ( ~ 104 hours/year ) Acceleration Factors Temperature Voltage

59 Introduction to Reliability (cont'd)
Most failure mechanisms can be modeled using the Arrhenius equation. ttf - time to failure (hours) C - constant (hours) EA - activation energy (eV) k - Boltzman's constant (8.616 x 10-5eV/°K) T - temperature (ºK) ttf = C • e EA/kT

60 Integrated Circuit Reliability Historical Perspective
Application Reliability Apollo Guidance Computer < 10 FITs Commercial (1971) Hours Military (1971) 2,000 Hours High Reliability (1971) 10,000 Hours SSI/MSI/PROM (1976) FITs MSI/LSI CICD Hi-Rel (1987) FITs

61 Actel FPGAs Technology FITS # Failures Device-Hours (m)
2.0/ x 107 x 108 x 108 x 108 x 107 x 107 RTSX x 107 x 107 x 107 Dropped some references in transferring slides 2.0/1.2 Data: ACT 1010/1020 Reliability Report S. Chiang and K. Hayes April 1990

62 Xilinx FPGAs XC40xxXL XCVxxx Static: 9 FIT, 60% UCL
Dynamic: 29 FIT, 60% UCL XCVxxx Static: 34 FIT, 60% UCL Dynamic: 443 FIT, 60% UCL

63 UTMC and Quicklogic FPGA UT22VP10 Antifuse PROM < 10 FITS (planned)
Quicklogic reports 12 FIT, 60% UCL UT22VP10 UTER Technology, 0 failures, 0.3 [double check] Antifuse PROM 64K: 19 FIT, 60% UCL 256K: 76 FIT, 60% UCL

64 Actel FIT Rate Trends

65 Thermal Thermal Analysis Basics Summary of Package Characteristics
Package Considerations Cavity Up/Down Heat Sinks

66 Thermal Performance Package modeled as a resistance
Junction temperature the critical parameter Often derated to ~ 100 ºC tJ = P • J-C tJ = Junction temperature in ºC P = Power in watts J-C = thermal resistance, junction to case, in ºC/watt

67 Thermal Performance - Devices J-C for Flight Devices in ºC/watt
Ceramic Pin Grid Array PG PG PG PG PG Notes: 1These packages are cavity down. 2With embedded heat spreader 3Estimated 4Typical Ceramic Quad Flat Pack CQ CQ CQ CQ CQ CQ Other PQ /3.82 PQ HQ CG

68 Die Up or Down?

69 CQFP256 w/ Heat Sink

70 Speed/Performance Basic Delay Model and Components Sample Delays
Examples from different families Hard-wired Structures Routing Arithmetic Logic

71 Antifuse Delay Model Tau = Resistance * Capacitance

72 Note: These numbers are approximate and work on better numbers is in progress.
UTMC, for PAL and PROM, has about 8 to 10 fF.


74 Model Direct Connect Fast Connect
Hardwired Structures Actel Routing Model Direct Connect Fast Connect (ns) (ns) RT54SX RT54SXS Virtex Carry Chain TBYP (CIN to COUT) ps, max

75 Power Consumption Power Basics Quiescent (Static) Current
Dynamic Current Per logic module Clock tree

76 Power - Basics Power = Voltage * current = V i Voltage is constant
Current = Static + Dynamic Static current: leakage, pullup resistors, DC loads Dynamic Power = kv2f k: constant often referred to as CEQ f: frequency


78 Device (Array) Quiescent Current1
Device Voltage Typical Spec Level Type (V) ICC (mA) ICCMAX(mA) A500K < Orion-4K RT < RT1280A < RT14100A < RT54SX < RT54SX32S < UT XQR40xxXL XQV XQV XQV XQV AT6010 1No DC Loads 2Commercial Specification XQV600 Lot Data (mA)1 lot # min mean max 1commercial or industrial worst-case, checking

79 PROM Device Current1 Device Voltage Standby Dynamic @F (MHz)
Type (V) ICC (mA) ICCMAX(mA) UT28F UT28F < 197A 1Specification levels 2.5 mA/MHz 3BAE Systems (formerly Lockmart) 32kx8 PROM

80 Representative Dynamic Power Numbers
A1280/A1280XL Power (mW) F(MHz) Module Input Output Clock Total ,440 ,159 , ,879 Predicting the Power Dissipation of Actel FPGAs Actel Corp, 1996

81 Preliminary

82 A Brief Introduction to Radiation and Programmable Devices

83 Types of Radiation Effects
Total Dose Single Event Effects (SEE) Single Event Upset (SEU) Multiple Bit Upset (MBU) Single Event Latchup (SEL) Single Event Transient (SET) Antifuse and Rupture Loss of Functionality Snap back Protons Miscellaneous

84 Total Dose

85 Recombination, Transport, and Trapping of Carries

86 Typical TID Run

87 TID Run - Runaway

88 TID Capability vs. Feature Size

89 Process Mods m

90 Single Event Upset (SEU)

91 From Aerospace

92 Cross Section versus LET Curve
From Aerospace

93 Act 2 SEU Flip-Flop Data

94 XQR4036XL SEU Cross Section
From Lum

95 Single Event Latchup (SEL)

96 Latchup Basics From Harris

97 SEL - QL3025 0.35 m BNL 02/98 S/N QL1 Run T2 VBIAS = 5.0V, 3.3V
0 Deg LET = 18.8 MeV-cm2/mg

98 Antifuse and Rupture

99 Comparison of Rupture Currents
Technology Development Vehicle Amorphous Silicon Antifuse Rupture ONO Antifuse

100 ONO Antifuse Breakdown - FA
Mag = 5X Mag = 20X Mag = 100X

101 Protons

102 ICC Damage During Proton Testing ASIC and Antifuse FPGA
Note: Different scales for each run.

103 RH1280 Proton Upsets From Lockheed-Martin/Actel

104 Summary and Some “Words of Wisdom”

105 FRAM Memory Functionality Loss During Heavy Ion Test
Strip chart of FM1608 (research fab) current during heavy ion irradiation. The device lost functionality during the test while the current decreased from it's normal dynamic levels of approximately 6.3 mA to it's quiescent value, near zero. The device recovered functionally and operated normally throughout the latter part of the test. This effect was seen at least three times during the limited testing of this device.

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