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GUSTECH presents: A micro-Course on SPI 4 Ultra-320.

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Presentation on theme: "GUSTECH presents: A micro-Course on SPI 4 Ultra-320."— Presentation transcript:

1 GUSTECH presents: A micro-Course on SPI 4 Ultra-320

2 Micro-Course on Ultra320; GUSTECH; v4 July Ultra-320 Topics Overview of U320 & T10 Documents Inquiry Information PPR Message & Negotiation Details Physical Interface Enhancements A few details on Training & Flow Control Information Units Update A few Mode Pages Assumes working knowledge of all prior SCSI technology

3 Micro-Course on Ultra320; GUSTECH; v4 July U320 Main Features & T10 Doubles transfer rate of U160 (SPI-3) via: Bus signaling enhancements Implementation of Information Units and addition of optional Read Streaming Implementation of Quick Arbitration Many others Project 1365D This document is based upon SPI-4, revision 10; 6 May 02 Also refer to SAM, SPC, and appropriate Device Specific Command Documents

4 Micro-Course on Ultra320; GUSTECH; v4 July Inquiry Information Who are you & what do you do? SPI-4 Version Descriptor Codes: –0B40 no version claimed –0B56 ANSI INCITS x –0B54 T10/1365D rev 7 –0B55 T10/1365D rev 9 –0B59 T10/1365D rev 10 Byte(s)Inquiry data (field, function) 6ADDR16 in bit 0, and others 7WBUS16, SYNC, and others 56ST/DT Clocking, QAS & IUS 58 & 59SAM compliance Descriptor Code 60 & 61SPI compliance Descriptor Code (SPI-4) 62 & 63Protocol compliance Descriptor Code 64 & 65SPC compliance Descriptor Code (SPC-3) 66 & 67Device Command Set code (SBC-2) 68 & 69Version Descriptor Code #6 70 & 71Version Descriptor Code #7 72 & 73Version Descriptor Code #8 Reference SPC-3, rev. 8, tables 57 & 63

5 Micro-Course on Ultra320; GUSTECH; v4 July Inquiry Information Who are you & what do you do? Byte(s)Inquiry data (field, function) 6ADDR16 in bit 0, and others 7WBUS16, SYNC, and others 56ST/DT Clocking, QAS & IUS 58 & 59SAM compliance Descriptor Code 60 & 61SPI compliance Descriptor Code (SPI-4) 62 & 63Protocol compliance Descriptor Code 64 & 65SPC compliance Descriptor Code (SPC-3) 66 & 67Device Command Set code (SBC-2) 68 & 69Version Descriptor Code #6 70 & 71Version Descriptor Code #7 72 & 73Version Descriptor Code #8 Reference SPC-3, rev. 8, tables 64, 65 & 66 ADDR16=1 supports ID[15:0] WBUS16=1 supports DB:15:0] SYNC=1 supports synchronous data transfers CLOCKING=11 supports both ST & DT transfers QAS=1 supports Quick Arbitration and Selection IUS=1 supports Information Unit transfers

6 Micro-Course on Ultra320; GUSTECH; v4 July Parallel Protocol Request BIT BYTE Extended Message (01h) 1 Extended Message (additional) Length (06h) 2 Parallel Protocol Request (04h) 3 Transfer Period Factor = 08h for Fast-160 Note: Fast-160 data is latched every 6.25nS 4 reserved 5 REQ/ACK OFFSET 6 Transfer Width Exponent = 1 for WIDE 7PCOM P_EN RTIRD_ST RM WR_FL OW HOLD_ MCS QAS_R EQ DT_RE Q IU_RE Q Reference SPI-4, rev. 10, table 71 Remember: DT is WIDE only, always Remember: REQ/ACK OFFSET = 0 means Asynchronous

7 Micro-Course on Ultra320; GUSTECH; v4 July Parallel Protocol Request details Precompensation enable Retain training information Read streaming and read flow control enable Write flow control enable Hold margin control settings QAS enable request DT clocking enable request Information units enable request BIT BYTE PCOM P_EN RTIRD_ST RM WR_FL OW HOLD_ MCS QAS_R EQ DT_RE Q IU_RE Q Reference SPI-4, rev. 10, table 9

8 Micro-Course on Ultra320; GUSTECH; v4 July Parallel Protocol Request details Precompensation enable=1 (set by OTHER SCSI device) indicates that the device receiving this bit set to 1 should enable its Precompensation Transmitters (CONTROL BIT) Retain training information=1 device can save Training Information and the Target does NOT need to retrain on each connection Read streaming and read flow control enable=1 Target should enable read streaming and read flow control Write flow control enable=1 Target should enable write flow control during write streaming BIT BYTE PCOM P_EN RTIRD_ST RM WR_FL OW HOLD_ MCS QAS_R EQ DT_RE Q IU_RE Q Reference SPI-4, rev. 10, sections through

9 Micro-Course on Ultra320; GUSTECH; v4 July Parallel Protocol Request details Hold Margin Control Settings=1 target should hold any margin control settings with the margin control subpage of the port control mode page QAS enable request=1 is a request that Quick Arbitration and Selection be enabled DT clocking enable request=1 is a request that DT clocking be enabled Information Units enable request=1 is a request that Information Unit Transfers be enabled BIT BYTE PCOM P_EN RTIRD_ST RM WR_FL OW HOLD_ MCS QAS_R EQ DT_RE Q IU_RE Q Reference SPI-4, rev. 10, sections through Any change in the negotiated state of IU_REQ, the target shall: Abort all tasks for that initiator and go to BUS FREE phase

10 Micro-Course on Ultra320; GUSTECH; v4 July Parallel Protocol Request details VALID Combinations when Transfer Period=08h: PCOMP_EN = 0 or 1; RTI = 0 or 1; RD_STRM = 0 or 1; WR_FLOW = 0 or 1; HOLD_MCS = 0 or 1; QAS_REQ = 0 or 1; DT_REQ=1; IU_REQ=1 BIT BYTE PCOM P_EN RTIRD_ST RM WR_FL OW HOLD_ MCS QAS_R EQ DT_RE Q IU_RE Q Reference SPI-4, rev. 10, table 11 Remember: DT is WIDE only, always Remember: REQ/ACK OFFSET = 0 means Asynchronous Any change in the negotiated state of IU_REQ, the target shall: Abort all tasks for that initiator and go to BUS FREE phase

11 Micro-Course on Ultra320; GUSTECH; v4 July pre-U320 Data Clocking 20h39h15hDEh05h3Ch69hF7h DB[7-0], driven by Target or Initiator Single Transition Data Phase on Narrow Bus P0 = Odd Parity REQ or ACK 9683h31D0h6931h03FBh9655hfillCRC Double Transition Data Phase on Wide Bus with CRC available P_CRCA = parity or CRC Available DB[15-0], driven by Target or Initiator REQ or ACK U160s Data Group Transfers example Reference SPI-4, rev. 10, figure 5 DT DATA IN shown

12 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING DB[15-0], driven by Target or Initiator REQ or ACK Reference SPI-4, rev. 10, figure 8 View at the transmitting device It is up to the receiving device to adjust all signals to match synchronous DT DATA waveforms as depicted on the bottom of slide 11 Lets see how this is made possible… 6.25nS 12.5nS 80MHz

13 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details View at the transmitting device View at the receiving device REQ or ACK any DBx any DBy any DBz Waveforms Signal rounding Amplitude reduction Signal skew

14 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details Reference SPI-4, rev. 10, figure 9 Playing Pieces LVD Transmitters Precompensated Drivers mux Data CRC Buffer This is only a partial model; not actual circuitry Transmitting SCSI DEVICE Receiving SCSI DEVICE Optional Signal Adjustment Skew Compensation Clock Shifter Receivers Buffer SCSI Bus Per signal line: If changing states (0 to 1, or 1 to 0) then use strong drive; if not changing states, use weak drive open loop compensation & Table 32 for Precompensation

15 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details Receiver Equalization with Filtering Adaptive Active Filter Skew Compensation Clock Shift REQ or ACK any DBx any DBy any DBz Waveform Restoration Reference SPI-4, rev. 10, figure 10 Tunedwith trainingtraining Adjustable, Closed-loop amplifier followed by a Steep-rolloff Low-pass filter

16 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details DT DATA IN: Initiators Receiver Training Reference SPI-4, rev. 10, Section Section A Training: DOG lines = DT Data IN Signal group ALL= P_CRCA, P1 & DB[15:0] Section B Training: Since the ALL signals are repeating as: … the precompensation drivers will be alternating between strong & weak Section C Training: REQ P1 DB[15:0] & P_CRCA Repeating pattern: … Total of 8 sets of patterns (only 5 shown) 800nS = 128 transfers P1 phase change will signal valid data NOTE: See section for DT DATA OUT phase training technique

17 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details P1 is now used to indicate the change of the data validity state by reversing the phase (appears as a lack of a change in state) of the (normally free running) P1 coincident with REQ or ACK assertion edges (slide 18 example) P_CRCA asserts when the current SPI data stream IU is the last SPI data stream IU of the current read or write stream Read flow control is mandatory if the optional read streaming is enabled (RD_STRM=1). The mandatory write streaming uses write flow control if enabled (WR_FLOW=1) Flow Control Reference SPI-4, rev. 10, Sections & & table 39

18 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details DT DATA IN: P1 Data Validity Signaling ex. Reference SPI-4, rev. 10, Section , & Figure 79

19 Micro-Course on Ultra320; GUSTECH; v4 July Double Transition PACING details Have explored just some of the techniques used to ensure the highest signal quality possible U320 uses CRC32 data integrity checking at the end of each Information Unit to verify the information is correct

20 Micro-Course on Ultra320; GUSTECH; v4 July Cyclic Redundancy Check Byte 1 Byte 0 Byte 3 Byte 2 Bit: DATA Transmission Wide Bus time Byte 0 Byte 1 Byte 2 Byte 3 Bit: Bit: Byte 0 Byte 1 Byte 2 Byte 3 Bit: Bit: Bit-Swap on Byte Boundaries Bit-Swap on Byte Boundaries CRC 0 CRC 1 CRC 2 CRC 3 Bit: Bit: Bit: Bit: CRC 0 CRC 1 CRC 2 CRC 3 CRC Calculation on 32-bit Boundaries CRC Transmission CRC 1 CRC 0 CRC 3 CRC 2 Bit: Wide Bus CRC Generation followed by Bit (1s complement) Inversion End of Data Reference SPI-4, rev. 10, Figure 80

21 Micro-Course on Ultra320; GUSTECH; v4 July Cyclic Redundancy Check The 32-bit generator polynomial used, that equals 104C11DB7 h is: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 The 32-bit unique remainder, that equals C704DD7B h is: x 31 + x 30 + x 26 + x 25 + x 24 + x 18 + x 15 + x 14 + x 12 + x 11 + x 10 + x 8 + x 6 + x 5 + x 4 + x 3 + x + 1 Total BytesData Pattern Sent in Data GroupWord 1 CRCWord 2 CRC 32 00h, 00h for all words 55AD h 190A h 32 FFh, FFh for all words AB0B h FF6C h 32 00h, 01h, 02h, 03h, 04h,..., 1Fh 7E8A h 9126 h CRC Test Cases: Reference SPI-4, rev. 10, Section

22 Micro-Course on Ultra320; GUSTECH; v4 July Quick Arbitration Optional method of transferring SCSI bus control without an intervening BUS FREE Three step process for implementation: 1.Discovery of support of QAS ( Inquiry CDB & Data ) 2.Negotiation for QAS usage ( PPR MSGs OUT & IN ) 3.Execution of QAS via QAS REQUEST message IN and the new & very unique protocol –Saves approximately 2uS of overhead per unique I/O process –Targets shall implement the Fairness Algorithm (see Appendix B) –Problems include bus starvation Reference SPI-4, rev. 10, Section

23 Micro-Course on Ultra320; GUSTECH; v4 July Quick Arbitration DB[7-0] T6 55h = QAS REQUEST REQ T6 ACK I7 DOG T6 MSG IN Phase BSY T6 SEL QAS REQUEST actuates disconnection of T=6 from I=7 logic levels depicted HiZ 90nS max HiZ 90nS max HiZ 90nS min, 200nS max 90nS min 25h T0, T2, & T5 Arbitrating 20h T5 wins quick Arbitration 1uS min Decide winner HiZ T5 drives SEL HiZ T6 releases Within 200nS T0 & T2 release Within 200nS Normal RESEL phase follows after 1uS delay Reference SPI-4, rev. 10, Section ? nS DT DATA Phase REQ & ACK not shown for brevity and extreme simplification

24 Micro-Course on Ultra320; GUSTECH; v4 July Information Units PACKETIZED SCSI Method of transferring SCSI bus Information using negotiated Synchronous Transfer rates and Wide bus widths (shall use for Pacing U320) Three step process for implementation: 1.Discovery of support of IU (Inquiry CDB & Data ) 2.Negotiation for IU usage (PPR MSG OUT & IN ) 3.Execution of Information Units phases using DT DATA IN and DT DATA OUT phases

25 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI details Four types of SPI Information Units: 1.L_Q = contains L_Q NEXUS information for existing I_T NEXUS and is always paired with one of the following : 2.COMMAND = single, last or multiple commands with task attributes and management flags (messages) for unique I_T_L_Q NEXUS; 3.DATA = DT DATA IN, DT DATA OUT, DT STREAM DATA IN, and DT STREAM DATA OUT for unique I_T_L_Q NEXUS; 4.STATUS = auto-sense data with status, and packetized failure codes for unique I_T_L_Q NEXUS. Reference SPI-4, rev. 10, Section 14.1 & others cited above Section Section Section Section Section

26 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit normal progression SPI L_Q IU Establish I_T Nexus Arbitration/Selection Completes Nexus: I_T_ L_Q SPI COMMAND IU SPI DATA IU SPI STATUS IU Includes Task Attributes and Management Flags; single, multiple & last commands Includes DATA IN and DATA OUT, STREAMING DATA IN, and STREAMING DATA OUT Includes Auto-sense = Error sense data, and Packetized failure codes NOTE: All four IU types terminate their transfers with iuCRC (described earlier), which can also occur at specified intervals in the transfers. Reference slide 20. Paired with: Paired with: Paired with: If more commands If more data If more data or status

27 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details After I_T NEXUS, logical connections, disconnections and reconnections are used, changing L_Q values as needed Logical disconnections SHALL occur ( back to just the I_T NEXUS ) at the completion of any: 1.Each SPI command IU 2.Each SPI status IU 3.Each SPI data IU 4.Any SPI L_Q if data length = zero; and 5.The last SPI data stream IU –if there are no phase changes to MSG OUT or MSG IN –If a change to MSG IN or OUT occurs, then existing I_T_L_Q NEXUS is maintained Reference SPI-4, rev. 10, Section 14.2

28 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit Phase Sequences overview BUS FREE DT DATA MESSAGE IN MESSAGE OUT RESELECTIONSELECTION ARBITRATION Hard Reset or Protocol Error Reference SPI-4, rev. 10, Figure 83 Slides 29 32

29 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit Sequence during initial connection SELECTION SPI L_Q (always Init to Targ) (logical connect) SPI COMMAND (always Init to Targ) (logical disconnect) BUS FREE (unexpected physical disconnect) BUS FREE DT DATA IN MSG IN MSG OUT (physical disconnect ) (QAS or WDTR) (to SPI L_Q/DATA or SPI L_Q/STATUS) I_T_L_Q Nexus remains in place I_T Nexus coming in I_T Nexus leaving I_T Nexus is gone here Can be many commands Attention Condition Reference SPI-4, rev. 10, Figure 85 Asynchronous Narrow

30 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit Sequence during data type transfers RESELECTION SPI L_Q (always Targ to Init) (logical reconnect) SPI DATA (logical disconnect) BUS FREE DT DATA IN MSG IN MSG OUT (physical disconnect ) (to SPI L_Q/DATA or SPI L_Q/STATUS) I_T_L_Q Nexus remains in place I_T Nexus coming in I_T Nexus leaving Initiator treats as having received a DISCONNECT MSG IN; I_T Nexus is gone here (data pointer saved) (data pointer restored) DT DATA IN from SPI STATUS or DATA DT DATA OUT from SPI COMMAND or DATA Attention Condition DT DATA OUT or DT DATA IN Reference SPI-4, rev. 10, Figure 86

31 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit Sequence during data stream type transfers RESELECTION SPI L_Q (always Targ to Init) (logical reconnect) SPI DATA (logical disconnect) BUS FREE DT DATA IN MSG IN MSG OUT (physical disconnect ) (to SPI L_Q/DATA or SPI L_Q/STATUS) I_T_L_Q Nexus remains in place I_T Nexus coming in I_T Nexus leaving I_T Nexus is gone here (data pointer saved) (data pointer restored) DT DATA IN from SPI STATUS or DATA DT DATA OUT from SPI COMMAND or DATA Attention Condition DT DATA IN or OUT Reference SPI-4, rev. 10, Figure 87

32 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI Information Unit Sequence during status transfers RESELECTION SPI L_Q (always Targ to Init) (logical reconnect) SPI STATUS (always Targ to Init) (logical disconnect) BUS FREE DT DATA IN MSG IN MSG OUT (physical disconnect ) (to SPI L_Q/DATA) I_T_L_Q Nexus remains in place I_T Nexus coming in I_T Nexus leaving I_T Nexus is gone here (data pointer restored) MSG OUT DT DATA OUT from SPI COMMAND or DATA Attention Condition DT DATA IN from SPI DATA (to QAS) Reference SPI-4, rev. 10, Figure 88 Data Length = 0 (no status follows) (See Section )

33 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details BYTES:FUNCTION 0TYPE (of IU following) 1Reserved 2-3TAG (like Q-tag) 4-11Logical Unit Number (four levels) 12Reserved Data Length * 16-17Reserved 18-19iuCRC Interval 20-23iuCRC CODE:TYPE: 01hLast Command 02hMultiple Command 04hData 05hData Stream 08hStatus All othersreserved Table 54 – SPI L_Q IUTable 55 – TYPE SPI L_Q Information Unit Details iuCRC Interval is the length in bytes of the data to be sent before an iuCRC is transferred. If zero, then only one iuCRC shall occur at the end of the SPI Information Unit. TAG is a 16-bit unsigned integer, (TAG Queue Number) Four levels of LUN are defined in SAM-2. Single level LUN (00-FF) is found in Byte 5. Reference SPI-4, rev. 10, Section BIDI Direction: byte 16, bits 7 & 6: per SPI-4, rev. 10, table 56 * Length of IU that follows, including per stream size: Initiators comand data length is 14h 90h.

34 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI COMMAND and DATA Information Units Details BIT BYTE reserved 1 Task Attribute 2Task Management Flags (messages out) 3Additional CDB LengthRDDATAWRDATA 4-19Command Descriptor Block (CDB) 16-bytes 20-nAdditional CDB (if needed – Group 3 CDBs) N+1->N+4iuCRC Table 51 – SPI COMMAND IU CODEDESCRIPTION: 000bSIMPLE task 001bHEAD of Queue task (BULLY) 010bORDERED task 011bReserved 100bACA task 101b – 111b reserved Table 52 – Task Attribute CODEDESCRIPTION: 00hNo task management for task 01hAbort Task ( MSG 0D h ) 02hAbort Task Set ( MSG 06 h ) 04hClear Task Set ( MSG 0E h ) 08hLogical Unit Reset ( MSG 17 h ) 20hTarget Reset ( MSG 0C h ) 40hClear ACA ( MSG 16 h ) Table 53 – Task Management Flags BYTEFUNCTION 0 -> NData N+1->N+4iuCRC SPI DATA IU Tables 57 & 58 in SPI-4 Reference SPI-4, rev. 10, Sections (command) & (data) Remainder of IU ignored if code is not 00h NO untagged CDBs

35 Micro-Course on Ultra320; GUSTECH; v4 July Packetized SCSI more details SPI STATUS Information Unit Details BIT BYTE reserved 2 Reserved for FCPSNSVALIDRSPVALID 3STATUS 4-7SENSE DATA LIST LENGTH (n-m) 8-11Packetized Failures List Length (m-11) 12-mPacketized Failures (see Tables 60 & 61) 1+m -> nSENSE DATA n+1 -> n+4iuCRC Table 59 – SPI STATUS Information Unit BYTESFUNCTION 0-2reserved 3Packetized Failure Code Table 60 – Packetized Failures Field CODESDESCRIPTIONCODESDESCRIPTION 00hNO failure or Function Complete04hTASK function not supported 01hReserved05hTASK function failed 02hCOMMAND IU fields invalid06hInvalid TYPE code received in L_Q IU 03hreserved07hIllegal request received in SPI L_Q IU Table 61 – Packetized Failure Codes Reference SPI-4, rev. 10, Section

36 Micro-Course on Ultra320; GUSTECH; v4 July Mode Pages for SPI-4 #02: Disconnect – reconnect page #18: Logical Unit Control page #19: Port Control page #01: Margin Control #02: Save training configuration value #03: Negotiated Settings #04: Report transfer capabilities #FF: Return all supported subpages Reference SPI-4, rev. 10, Section subPages Byte 0, Bit 6: SPF=1 for the Subpage format; subpage # is then in byte 1

37 Micro-Course on Ultra320; GUSTECH; v4 July Port Control Mode Page Margin Control parameters include: –Driver Strength, Driver Asymmetry, Driver Slew Rate, & Driver Precompensation. Saved Training Configuration parameters include 4byte values for each of: DB[15:0], P_CRCA, P1, BSY, SEL, RST, REQ, ACK, ATN, C/D, I/O, and MSG #01: Margin Control #02: Save training configuration value #03: Negotiated Settings #04: Report transfer capabilities #FF: Return all supported subpages Reference SPI-4, rev. 10, Sections & ; & Tables 87 & 89

38 Micro-Course on Ultra320; GUSTECH; v4 July Port Control Mode Page Negotiated Settings parameters include: Transfer Period Factor, Req/Ack Offset, Transfer width, protocol options, Transceiver mode, & Sent/Received PCOMP_EN flags Report transfer capabilities includes: Minimum transfer period factor, Maximum REQ/ACK Offset, Maximum transfer width exponent, and protocol option bits supported. #01: Margin Control #02: Save training configuration value #03: Negotiated Settings #04: Report transfer capabilities #FF: Return all supported subpages Reference SPI-4, rev. 10, Sections & ; & Tables 90 & 92 Transceiver Mode: 00 = unknown; 01 = Singled Ended; 10 = Low Voltage Differential; & 11 = High Voltage Differential

39 Micro-Course on Ultra320; GUSTECH; v4 July SPI-4 Annex List: A: Additions needed for LVD SCSI Drivers and Receivers B: SCSI Bus Fairness C: Nonshielded connector alternative 4 D: warm Plugging E: SCSI Cable Testing F: Simple Expander Requirements G: Expander Communication Protocol H: Connecting different widths I: Transmission lines for SE Fast- 20 J: Measuring SE pin capacitance K: SCSI ICONs L: Backplane construction guidelines M: SPI-4 SCSI-2 terminology mapping Reference SPI-4


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