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Copyright © 2006 MIPS Technologies, Inc and First Silicon Solutions. All rights reserved. At the core of the user experience ® Getting System On Silicon.

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Presentation on theme: "Copyright © 2006 MIPS Technologies, Inc and First Silicon Solutions. All rights reserved. At the core of the user experience ® Getting System On Silicon."— Presentation transcript:

1 Copyright © 2006 MIPS Technologies, Inc and First Silicon Solutions. All rights reserved. At the core of the user experience ® Getting System On Silicon to market Faster ® Request-Response Trace for Bus Performance Analysis Dr. Neal Stollon Jan. 2007

2 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Introduction MIPS Technologies is Leader in High Performance Embedded RISC Processors MIPS32 ® 34K TM Multi-threaded RISC Processor SoC-IT Platforms Best in class applications and tools eco-systems FS2 is Instrumentation IP and Tools Division of MIPS On-Chip Instrumentation (OCI ® ) Leadership Integrated Trace and Analysis Solutions for Embedded Processor, Logic and On- Chip Bus IP Leading edge on-chip analysis tools for MIPS based systems – RRT performance analysis as only one example

3 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved SoC Analysis and Debug Issues Visibility and optimization is crucial to embedded design success Difficult to fix/optimize what you can not see - Unexpected on-chip Inter-relationships not always intuitive System on Silicon Instrumentation Requirements Visibility - into non-observable sub-system interfaces –On-chip analysis complements EDA verification Interoperable control with processor debug capabilities –Cross-triggering, synchronization for full view of problems Reasonable gate size and trace speeds –Range of features configurable to system requirements IO requirements –Leverage existing debug interfaces i.e. JTAG –High performance IO allows more extensive trace

4 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved SoC On-Chip Instrumentation Evolution Debug- Difficulty (gates/pins ) ICE / BDM Analysis Tools JTAG (Scan, BIST Run Ctrl) System Level Embedded Instrumentation Embedded Processor / Logic Trace 1980s1990s2000s Embedded Systems ASICS SoC (RISC+IP +RAM) Platform SoC (Multi-Core) 50K 20K 8K 2.5K 1K Complexity of Embedded Analysis requirement keeps increasing Gates increase geometrically - Pins increase linearly Significant bandwidth for leading architectures More complex analysis needs Instrumentation The New Frontier EJTAG Navigator RRTPDtrace MIPS Solutions

5 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Modeling and Verification Abstraction System Analysis Focus Core IP Modeling and Verification Abstraction System Initialization Instruction Level/ Bus Functional Hardware Simulation Application Software RTL Diagnostics RTOS Integration ESL Focus on Hardware Bugs Focus on Software Bugs Point were Hardware is assumed working Hardware Prototype/Emulation Software Debugger System platform Multi-core Integration issues Pre-silicon – EDA based analysis Post-silicon – In System centric analysis System Platform

6 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Drivers for Request Response Trace Other Layers Initiator Agent IA TA IA dedicated links OCP socket OCP socket AXI socket bridge AHB socket bridge OCP socket bridge APB socket OCP socket AHB socket XBar fabric RP Target Agent IA PP TA bridge PP Shared Link fabric TA RP bridge Source: 2006 Sonics, Inc. Analysis of complex on chip interconnection networks Need to analyze transfer/response latencies Lower overhead analysis for critical information

7 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved RRT as a Performance Analysis Trace System MIPS OCP IF Other core OCP IF Selected IP IF processor trace Synch signals Mictor 2 JTAG port System Trace Probe RRT agent – OCP capture, filter, format RRT OCP agent - RRT custom agent - b RRT AHB agent - Navigator RRT Trace Port Combiner/ Scheduler trace funnel DMA AHB IF Multicore Processor trace Mictor 1 Trace funnel provides prioritized transfers Agents provide in line filtering formatting of bus data HOST PC (Win/Linux) Analyzer tools USB Ethernet

8 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Point-to-point Timing A to B event timing measurements: event A starts counter, event B stops counter read out duration via JTAG port, or save counter values into trace then zero counter in single cycle Benefit: measure loop times of algorithms, task executions, interrupt handlers, waiting for resource System Performance Measurements Trace history of counted values Observe change in measured values over multiple occurrences Example: multiple durations between A-B events Benefit: see how loop times change over the real-time execution on system Trace Performance Profiling

9 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved System Level Performance Analysis Types of analysis that are important Measure activity - bus utilization, caches efficiency, co- processors, interrupts, peripheral device events Measure latencies - interrupts, bus access, DMA transfers loop times of processing network packets, DSP Blocks Monitoring bus bandwidth utilization, efficiency Caches hit/miss ratios, DRAM pages, processor stalls RRT provides Analysis of System operations Timestamping for interval measurements relative to real time Counter and trigger resources for real time event rates or duration measures

10 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved On Chip Performance Trace - RRT System Bus Fabric Other IP blocks (video, imaging... ) PDtrace EJTAG MIPS core Other IP JTAG & TRACE PORT (To SNP IO) Trace Funnel Cross Triggers JTAG TAP RR Trace Agents RR Trace Agents RR Trace Agents Selective trace capability Simple event monitoring Triggers, counters in probe Probe based Trace filtering and alignment Trace limited by Port Bandwidth

11 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved RRT Debug Flow RRT IP Integration design RTL files Trigger/ Trace Requirements Instrumented RTL files SYNTHESIS Place & Route To target Trace and post processing GUI Trace data (from SNP) VCD Export Analyzer configuration Instrumentation configuration file Customer EDA tools Environment

12 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Mobileye EyeQ2 Analysis Needs Complex automotive image processing IC 10 cores (MIPS 34K, DSPs, DMA) Complex OCP/AMBA system network Multi-layer Sonics SMX Complex memory subsystems Debug Performance and bottlenecks Analyze bus latencies and throughput Trace bus control transactions of 4 concurrent transactions (34K, DSP, DMA) Trace full address for any transaction Correlate Bus transactions to PDtrace Track active threads to bus operations Trace at least one image frame (>1 Gbyte) Low overhead debug solution (minimal buffering) Reduced operating speed OK Pins available for dual trace ports

13 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved RRT Instrumentation for Mobileye Request-Response Trace – Real time Bus Transaction Analysis Solution built around SNP 64 pin target interface –Allows processor and bus trace Deep (2 Gbyte) Probe Trace Buffer –Multi-frame trace Complex triggers, timestamps,... RRT agents and funnel IP Minimized on chip Logic Complex trace resources in probe Upgraded PDtrace for multicore trace Multicore PDtrace Funnel IP PDtrace/RRT Correlation in SW Request-Response delay analysis PDtrace/RRT Bus Correlation Mictor 1 Mictor 2 JTAG port FS2 System Probe RRT Agent (capture, filter, format) RRT Agent RRT Trace Port RRT Trace Funnel (combiner/ Scheduler) MIPS 0 (34K 2x OCP) MIPS 1 (34K 2x OCP) DMA (AHB) VCE (XB1 OCP) Multicore PDtrace Funnel/ Port

14 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved First Silicon Solutions Introduces System Navigator Pro Series of High Performance Trace Probes Next-Generation Hardware Platform Addresses SoC Debug and System-Level Verification PORTLAND, OR, Jan. 30, First Silicon Solutions (FS2), a division of MIPS Technologies, Inc. (NASDAQ: MIPS), today announced the production release of System Navigator Pro, a high performance high capacity trace probe family designed to address complex SoC debug and system-level verification....

15 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved New System Navigator Pro Probe System Navigator Pro (SNP) provides next generation probe technology for debug applications that require massive amounts of off-chip trace capture Supports all JTAG functions of Sys Nav probe 38-pin Mictor target IO (up to 2 per probe) –32 bits of trace data per Mictor connection Up to 2G byte deep trace buffer Supports trace bandwidth of up to 16 Gbps –Target interface speed up to 500MHz –USB 2.0 and 10/100/1G Ethernet PC interfaces Supports current MDI 3 rd party tools interface SNP provides value added analysis with –Malta boards –FPGA based prototyping environments –Systems Emulation tools System Level Debug Initiative Support Capture of large amounts of bus and processor data for post processing

16 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved System Debugger Environment Architecture Windows MABILib/MDILib DLL PC Interface Cross Trigger Common Tcl/Tk CLI FS2 System Navigator JTAG Probe 3 rd Party Source Level Debuggers MDI MIPS Processor Core PDtrace OCI EJTAG Bus Trace OCI JTAG Port Trace Port Optional Eclipse IDE GDB SDK Off-Chip On-Chip Trace RAM Trace Funnel BusTrace and Triggering GUI Bus Data FS2 In System Analyzer (ISA) - Standards based IDE Plug and play with all MDI complaint 3rd party tools User transparent concurrent debug access (many cores/many debuggers) Eclipse, Tcl/TK, MDI, XML, text based scripting and configuration

17 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved System Navigator Pro RRT support Provide correlated view of processor and bus operations latency measurements outside of core visibility Common views of core and system performance Migration to unified display and GUI

18 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved Trigger Trace from Applications or IP Processor operations can drive analysis operations ex. Cross-Triggering Bus Trace with MIPS Source Code Trigger bus trace from Breakpoint Use bus condition as breakpoint input

19 Copyright 2006 MIPS Technologies Inc. & First Silicon Solutions. All rights reserved On-Chip Instrumentation IP MIPS Processor Instruments Integrated Bus Analyzers Multi-Core debug Performance Analysis Application specific/custom debug blocks System Navigator Probes USB 2.0, Ethernet and ECP host PC connections 14-pin (EJTAG & on-chip PDTrace) or 38-pin Mictor (EJTAG & off-chip PDTrace) target connections Integrated with MIPS SDE software Low speed and RTCK support for emulation systems integration Software Tools and Interfaces Integrated w/MIPS GDB Complete EJTAG & PDTrace support On-chip and off-chips trace tools Performance Monitoring tools Supports 3 rd party debugger and RTOS interfaces FS2 = Comprehensive Debug Solutions


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