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– 1 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Active Filters

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Introduction – 2 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Filtering: most common linear time-invariant (LTI) signal processing function – selecting the signal bandwidth of interest (in reality neither linear nor time-invariant)… Categories: continuous time (CT), discrete time (DT) analog filter, digital filter (will focus on CT analog filters for this course) Frequency domain: low-pass (LP), high-pass (HP), band-pass (BP)… Time domain: impulse response, FIR, IIR…

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Simple RC Filter – 3 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Continuous-time, 1 st -order, one real pole, low-pass

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Simple RC Filter – 4 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Frequency responseImpulse response

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General Filter Specs – 5 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 More realistic: Magnitude response ω p, ω s, α p, and α s Phase response Ideal LPF: Non-causal Infinite complexity

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Example: 2 nd -order VTF – 6 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Continuous-time Where are the poles? (complex conjugate poles for maximum flatness) Low-pass, high-pass, or band-pass?

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Passive RLC Filter – 7 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 No active component (low power) Inductors are bulky and expensive to realize in ICs Values of R, L, and C will not track each other

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Active OP-RC Filter – 8 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Its active Inductor-less Area efficient Values of Rs and Cs and their time co.s wont track each other – may lead to RC time constant variations of as high as 20% RC time constant enters the VTF in product form – can be tuned for accuracy Assuming ideal op amps,

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Continuous-Time Integrator – 9 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Assuming ideal op amp,

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– 10 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Cascade Filter Design Biquads

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Cascade Filter Design – 11 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 For a real-coefficient H(s): 2 nd -order1 st -order Biquad: The leading minus sign in H bq (s) is only for convenience

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Special Cases of Biquad – 12 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Q Factor of Poles – 13 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Signal Flow Graph (SFG) for Biquad – 14 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Note: the partition of the biquadratic VTF is not unique

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OP-RC Implementation – 15 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Alternative SFG for Biquad – 16 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Recast H bq (s):

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Alternative OP-R-C Prototype – 17 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Cascade Filter Design – 18 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 For a real-coefficient H(s): 2 nd -order1 st -order Order of cascade determines the signal dynamic range Optimized using engineering rule of thumb or thru simulation

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Biquad Cascade Filter Design – 19 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Most flexible arrangement of cascade filter design Allow independent, non-interacting control of (ω 0, Q) for pole pairs Easy design Components need to be scaled for maximum DR and minimum component spread Pass-band sensitivity to capacitance variation is finite Ladder filter can achieve zero sensitivity

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– 20 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Scaling of Active Filter

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Typical Active Multi-Stage Filters – 21 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Initial component values may not be optimal...

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Freq. Response of Internal Nodes – 22 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Internal signal swings need to be large to max SNR But not too large such that op amps saturate (producing distortion)

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DR Scaling of i th Integrator (V i ) – 23 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 First find out the peak value of V i (ω), mostly done with simulation Then find out the ratio k i = V i,peak /V o,max Multiply all capacitors connecting at V i by k i : F i F i *k i, S ij S ij *k i, … Divide all resistors connecting at V i by k i : F i F i *k i, S ij S ij *k i, … Repeat for all internal nodes…

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After DR Scaling – 24 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Max internal signal swings all line up to V o,max

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Scaling for Min. Component Spread – 25 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Find out the smallest cap/res connected to X i – the summing node of A i determine the optimum scaling factor m i to minimize spread Multiply all capacitors connected to X i by m i : F i F i *m i, S ji S ji *m i, … Divide all resistors connected to X i by m i : F i F i *m i, S ji S ji *m i, … Repeat for all integrators…

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Scaling of Active Filter – 26 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 DR and min spread scaling do not take op-amp loading into account – lots of work if individual op amps are sized to meet the settling time constraint Upon the completion of scaling, simulation needs to be performed on the resulting filter to find out the overall SNR If SNR is lower than the spec, capacitors and op amps need to be scaled up and resistors scaled down to meet the SNR spec (think about how integrated output noise behaves)

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– 27 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Ladder Filter Design

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Motivation – 28 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Cascade filter design –Sensitive to component variations, especially high-Q poles Ladder filter design –Achieves zero sensitivity to component variations –Discrete CT LC filters with very high-Q poles are built with ladder structures over the years

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Ladder Filter – 29 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Doubly terminated reactance two-port network Delivers the optimum power matching in the passband |V out |/Z i = 0 for all Ls and Cs low sensitivity Reactance two-port

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State Space of Ladder Filter – 30 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Pick –V 1, -I 2, V 3 as the state variables for synthesis

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Signal Flow Graph (SFG) – 31 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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CT OP-RC Ladder Filter – 32 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Three free state variables three op amps A.k.a the leapfrog ladder structure

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Transmission Zeros – 33 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Transmission Zeros – 34 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Modified SFG with Derivatives – 35 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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OP-RC Ladder Filter w/ Derivatives – 36 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Derivative input paths implemented with capacitors

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– 37 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Other Active Filters

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Tow-Thomas Biquad – 38 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 [1] P. E. Fleischer and J. Tow, "Design formulas for biquad active filters using three operational amplifiers, Proceedings of the IEEE, vol. 61, pp , issue 5, Low sensitivity Non-interactive tuning property

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Design Equations for Tow-Thomas – 39 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Note: C 1, C 2, k 1, k 2, R 8 are free parameters

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Sallen-Key LPF – 40 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 OP-RC active filters are ideally insensitive to bottom-plate stray caps Sallen-Key is sensitive to bottom-plate parasitics at node A and B

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Design Equations for SK LPF – 41 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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Sallen-Key BPF – 42 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Still sensitive to parasitic capacitance at node A and B

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Design Equations for SK BPF – 43 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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– 44 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 MOSFET-C Active Filter

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MOSFET Resistor – 45 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 MOSFET in triode region is a variable resistor Compact, low parasitics compared to large-value resistors

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MOSFET Resistor – 46 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 But the large-signal response is quite nonlinear

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A Linear (Diff.) MOSFET Resistor – 47 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 MOSFET resistor is linear when driven by balanced differential signals!

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Rudell VGA + Mixer – 48 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 [2] J. C. Rudell et al., A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications, IEEE Journal of Solid-State Circuits, vol. 32, pp , issue 12, M9-M15 comprise the CMFB circuit Gain adjustment by varying I Gain

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MOSFET-C Integrator – 49 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Sources of M 1 and M 2 are ideally always equal-potential Fully differential circuit rejects the 2nd-order harmonic (and all even-order distortions) Triode resistance significantly depends on process (threshold, mobility, etc.), temperature, and V DD Filter response needs tuning =

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– 50 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Frequency Tuning

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Master-Slave Tuning – 51 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 M 1 -M 1 ' and C-C' are matched devices Master sets M 1 -C time constant to an off-chip reference thru f/b Slave integrator time constant follows that of the master Subject to device mismatch between the master and slave

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R eq Matching – 52 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 [3] R. Geiger, P. Allen, and N. Dinh, Switched-resistor filters - A continuous time approach to monolithic MOS filter design, IEEE Transactions on Circuits and Systems, vol. 29, pp , issue 5, 1982.

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R eq Matching – 53 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Charge from R is continuous but discrete from C r V C (t) should be sampled at the end of Ф2 and held before being applied to the MOSFET gate LPF can be used instead of ZOH, but error will be introduced

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Phase Locking – 54 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 [4] K. R. Rao, et al., A novel follow the master filter, Proceedings of the IEEE, vol. 65, pp , issue 12, [5] R. Geiger, P. Allen, and N. Dinh, Switched-resistor filters - A continuous time approach to monolithic MOS filter design, IEEE Transactions on Circuits and Systems, vol. 29, pp , issue 5, 1982.

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Phase Locking – 55 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Phase detector converts the phase difference b/t V 1 and V 2 into a pulse with bipolar average The trailing integrator keeps integrating when 0 holds

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Phase Locking – 56 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 = 0 holds for Δφ = 90º, -90º, … In steady state, V 2 leads V 1 by 90º Negative f/b sets the pole freq. of the HPF formed by C & R to ω ref Δφ = 90º

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CT Ladder Filter Tuning – 57 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall th -order Chebyshev-I all-pole continuous-time filter Integrators are realized by G m -C active structures

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G m -C Active Integrator – 58 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 Differential input with programmable gain constant G m /C

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Frequency Locking – 59 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013 [6] K.-S. Tan and P. R. Gray, "Fully integrated analog filters using bipolar-JFET technology," IEEE Journal of Solid-State Circuits, vol. SC13, pp , issue 6, 1978.

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VCO – 60 – Advanced Analog IC DesignProfessor Y. Chiu EECT 7326Fall 2013

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