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Alicia Klinefelter ECE 7332 Spring 2011 DIGITALLY CONTROLLED OSCILLATORS (DCO)

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 2

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Problems with analog implementation Design and verification Settling time 20 – 30 ms in CPPLLs 10 ms in the ADPLL Implementation cost Custom blocks Loop Filter High Leakage current Large capacitor (2) area Charge Pump Low output resistance Mismatch between charging current and discharging current Phase offset and reference spurs WHY ARE ADPLLS USEFUL? 3

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ALL-DIGITAL PLL (ADPLL) TOPOLOGY Time-to-Digital Converter (TDC) Digital Loop Filter Divider ref(t) DCO out(t) 4

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Architectures Delay chain structure sets resolution Mismatch causes linearity issues Resolution: want low quantization noise 5 ADPLL: TIME-TO-DIGITAL CONVERTER Time-to-Digital Converter (TDC) Digital Loop Filter Divider ref(t) DCO out(t) div(t) [1, Perrott]

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Compact area Insensitive to leakage 6 ADPLL: DIGITAL LOOP FILTER Time-to-Digital Converter (TDC) Digital Loop Filter Divider ref(t) DCO out(t)

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ADPLL: DCO Time-to-Digital Converter (TDC) Digital Loop Filter Divider ref(t) DCO out(t) 7 Replaces the VCO from analog implementations Consumes 50-70% of overall ADPLL power Generally consists of a digital controller implementing frequency acquisition algorithm and oscillator.

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Power Frequency Phase Noise Measured with respect to a frequency offset from the carrier The units, dBm/Hz, define noise power contained in a 1 Hz bandwidth Jitter LSB Resolution (ps) Tuning range Note: bit resolution is rarely mentioned Does not seem to have drastic impact on tuning range 8 METRICS

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 9

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Straightforward approach DAC + VCO Varactors used initially Problem with varactors: Capacitance not very linear with input voltage. linear For digital tuning, need flat regions. 10 EARLY ARCHITECTURES: ANALOG TUNING [3, Xu]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 11

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OSCILLATORS: RING OSCILLATOR 12

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OSCILLATORS: LC OSCILLATOR um [4, Thiel]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 14

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Weighted capacitor networks replaced varactors Concept of fine and coarse tuning introduced Coarse (binary weighted) lacks monotonicity Fine (unit weighted) has monotonicity but complex control 15 NOVELTY: FULLY DIGITAL TUNING

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To increase resolution, many systems use ΣΔ modulators for dithering the input to the unit caps. Unit cap determines gain of DCO Recall, ΣΔ modulators are oversampling converters and produces output pulses proportional to signal changes. Quantization noise effects Phase noise goes down as frequency increases 16 TECHNIQUE : DITHERING [1, Perrott]

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17 NOISE ANALYSIS: DITHERING H(s) x[n] y(t) [1, Perrott]

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18 NOISE ANALYSIS: DITHERING [1, Perrott]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 19

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Many traditional delay lines are simple inverters Chain of tri-state inverters in parallel Driving capability modulation (DCM) Changes the driving current of each delay cell by controlling number of enabled tri-state buffers/inverters Bad power, linearity DELAY CELLS: DCM 20

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Hysteresis delay cells (HDC) are relatively new in low power ( ). Trade off power and delay resolution. Fewer needed to acquire the delay of a many traditional delay cells. HDCs have wider operating range Control of driving current to obtain different propagation delay DELAY CELLS: HYSTERESIS 21 [2]

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Application: Wireless body area networks Relaxes phase noise requirement Oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture Each delay stages is ½ delay of previous 80um x 80um in 90nm CMOS 3.4MHz, 1V supply Presents two novel HDC topologies Improves power-to-delay and area-to-delay ratios 22 IMPLEMENTATION

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Uses different hysteresis cells for different tuning stages Need for decoder removed due to power of two delay Header and footer rarely turned on at same time Leads to voltage scaling of the cell with hysteresis 23 IMPLEMENTATION: DELAY CELLS [9]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 24

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As technology migrates, push towards standard cell implementations for portability. Goal: implement DCO in HDL Ring oscillators always used for synthesizeable DCO Limits implementation options Most delay cells inverters and NANDs Controllers simply digital logic ARCHITECTURE: STANDARD CELL 25

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Segmented delay line, hysteresis delay cells, and uses standard cells: ultra portable! 140uW MHz) with 1.47-ps resolution Segmented delay line power gating saves ~25-75% of power Dependent on operating frequency 26 PAPER HIGHLIGHTS [2]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 27

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New DCO tuning word (OTW) presetting technique to reduce settling time Three stages in ADPLL PVT calibration Frequency Acquisition Tracking (locked) Each mode is a search algorithm, each has its own scheme For ring oscillator, controller implemented in digital logic For LC oscillator, controller is capacitor bank 28 CONTROLLER: LOCKING TIME

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Paper [4] designed a new, faster locking algorithm for frequency acquisition. Locks in 18 clock cycles Binary search typically used 29 CONTROLLER: FASTER ALTERNATIVE [4]

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1.PFD produces gain and fast/slow pulse 2.Mux selects fast/slow gain value 3.Gain value like the charge pump 1.As DCO frequency differs more from target, gain increases 4.Use previous gain with new gain to determine new guess value 30 CONTROLLER: FASTER ALTERNATIVE [4]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 31

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1.9 GHz DCO in 0.13um technology 2 x 2mm 2 using 6 metal layers Supply voltage at 0.5V, 100uW power More device transconductance (g m ) is available for a given bias current Application: frequency synthesizer in wireless transceiver Between calibration, oscillator runs free until next tuning cycle (TX/RX) Other circuitry turned off No external components used (even with LC oscillator) 32 NOVELTY: SUBTHRESHOLD

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Differential NMOS only for high output swing for low input voltages Inductance Want high Q determines overall Q of system, startup current, and power consumption Used bondwire inductances Want 1fF LSB from caps, but a problem when wiring parasitics on same order of magnitude 33 OSCILLATOR: LC BASED [10]

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Capacitor matching a problem for small unit capacitors Varactors could work Need flat areas of curve Testing required to find input voltages of such areas Switched capacitor implementation using linear capacitors proposed Routing parasitics reduced 34 CHALLENGE: SMALL CAPACITORS [10]

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Basic Topology of All Digital PLLs (ADPLL) Where does the DCO fit in? Early Architectures Oscillator Background Current Research Seminal: All Digital Control [14] Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process Hysteresis Delay Cell [9] A Sub-10-μW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications Portability [2] An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications Frequency Acquisition and Locking [4] A 1.7mW all digital phase-locked loop with new gain generator and low power DCO Subthreshold Operation [10] A 100μW, 1.9GHz oscillator with fully digital frequency tuning Comparison of Results OUTLINE 35

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PowerOp. FreqVoltage 5.4uW3.4MGHz1 V 5.2uw3.89MHz1 V 8mW12.3MHz1.2 V 1.7mW20MHz1 V 166uW163.2MHz1 V 140uW200MHz1 V 110uW200mhZ0.8 V 75.9uW239.2MHz1 V 340uW450MHz1.8 V 1.7mW560MHz1.2 V 2.3mW800MHz0.9 V 23.3mW1GHz1.8 V 5.5mW5.6GHz0.7 V 36 DESIGN COMPARISONS: POWER

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37 DESIGN COMPARISONS: FREQ OFFSET

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38 DESIGN COMPARISONS: TUNING RANGE

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CPPSIM Tutorials [1, Perrot] PLL Digital Frequency Synthesizers [2, Perrot] PLL Voltage Controlled Oscillators All papers in the bibliography section of Wiki were used for plot generation Papers [2], [4], [9], [10], [14] addressed in presentation [3, Xu] Xu, L. (2006, May 18). Digitally controlled oscillator. Retrieved from [4, Thiel] Thiel, B.T.; Neyer, A.; Heinen, S.;, "Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS," Research in Microelectronics and Electronics, PRIME Ph.D., vol., no., pp , July RESOURCES

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Move to digital PLL implementations motivated by SoC applications New digital circuits in ADPLL: TDC, filter, DCO Ring oscillators versus LC oscillators Current Research Initial digital tuning with sigma-delta dithering Delay cells Portability Frequency acquisition algorithm Sub-threshold operation QUESTIONS? 40 OVERVIEW

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