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OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads Authors : Tao Li, John, L.K. Published in : Performance, Computing, and.

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Presentation on theme: "OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads Authors : Tao Li, John, L.K. Published in : Performance, Computing, and."— Presentation transcript:

1 OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads Authors : Tao Li, John, L.K. Published in : Performance, Computing, and Communications Conference, IPCCC th IEEE International Date of Conference : April , ,

2 1.Introduction 2.Experimental Methodology 3.User/OS I-Cache Accesses Characterization 4.OS-aware I-Cache Tuning 5.Power and Performance Evaluation 6.Conclusions / 30 2 Outline

3 Dynamic power dissipation Due to charging and discharging highly capacitive bit lines and sense amps Static power dissipation -> / Introduction

4 / 30 4

5 / app

6 Dynamic : OS-aware cache way lookup Static : OS-aware cache set drowsy mode / 30 6

7 Modified vision of SoftWatt SimOS OS: SGI-IRI 5.3 : 8-issue superscalar processor split L1 Instruct.,data cache unified L2 cache memory 15 application / Experimental Methodology

8 Vortex : database manipulation code Gcc : compiler code Sendmail : SMTP, 1KB~1.5MB Fileman : cp, rm, chmod, tar –cvf… …… OS activity ranges from 6% in compress,92% in fileman / application

9 / User/OS I-Cache Accesses Characterization OS instruc. User instruc.

10 / 30 10

11 A conventional 4-way set associative cache requires four tag comparisons and four data array read-outs for a cache access. Nevertheless, during user execution, performing tag comparisons and data array read-outs for OS cache lines are unnecessary and waste extra dynamic power / 30 OS-aware Cache Way Lookup

12 Cache way mode bit Processor status register(PSR) / 30 OS-aware Cache Way Lookup

13 / 30 OS-aware Cache Way Lookup

14 Once generated, they remain unchanged unless a cache line replacement. The processor switches mode / 30 OS-aware Cache Way Lookup

15 / 30 OS-aware Cache Way Lookup

16 Due to CMOS technology scaling, static power due to leakage current is gaining in importance in I-cache power dissipation. These make efforts at leakage control essential to maintain control of I-cache power on current and next generations of processors / 30 OS-aware Cache Set Drowsy Mode

17 State-preserving drowsy cache techniques.(L1) Gated-V dd technique.(L2) Cache way mode bit / 30 OS-aware Cache Set Drowsy Mode

18 / 30 OS-aware Cache Set Drowsy Mode

19 / 30 OS-aware Cache Set Drowsy Mode

20 / 30 OS-aware Cache Set Drowsy Mode

21 Access-biased classification / 30 OS-aware Cache Set Drowsy Mode

22 / 30 OS-aware Cache Set Drowsy Mode

23 OS-aware cache way lookup dynamic power user execution 29% OS execution 30% / Power and Performance Evaluation 30% dynamic power

24 dynamic power cache way access OS-aware cache way lookup 30% dynamic power power / Power and Performance Evaluation

25 Residency-based drowsy mode scheme 5% - 50% leakage power Access-based drowsy mode scheme cache drowsy state leakage power 37% leakage power / Power and Performance Evaluation

26 OS-aware cache set drowsy mode method <1% cache set drowsy mode cache set drowsy policies drowsy cache / Power and Performance Evaluation

27 / 30 27

28 I-cache user/OS I-cache dual-mode operation / Conclusions

29 OS-aware cache way lookup parallel tag comparison data array readout dynamic power OS-aware tuning CMOS static power OS-aware tuning dynamic power static power / Conclusions

30 Thanks for your listening / 30 30


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